SN54LS299

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8 位通用移位/存儲寄存器

產(chǎn)品詳情

Configuration Universal Bits (#) 8 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 25 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (μA) 53000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
Configuration Universal Bits (#) 8 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 25 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (μA) 53000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 20 167.464 mm2 24.2 x 6.92 CFP (W) 20 90.5828 mm2 13.09 x 6.92 LCCC (FK) 20 79.0321 mm2 8.89 x 8.89
  • Multiplexed Inputs/Outputs Provide Improved Bit Density
  • Four Modes of Operations:
    • Hold (Store)
    • Shift Left
    • Shift Right
    • Load Data
  • Operates with Outputs Enabled or at High Z
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for N-Bit Word Lengths
  • SN54LS323 and SN74LS323 Are Similar But Have Synchronous Clear
  • Applications:
    • Stacked or Push-Down Registers Buffer Storage, and Accumulator Registers

 
  • Multiplexed Inputs/Outputs Provide Improved Bit Density
  • Four Modes of Operations:
    • Hold (Store)
    • Shift Left
    • Shift Right
    • Load Data
  • Operates with Outputs Enabled or at High Z
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for N-Bit Word Lengths
  • SN54LS323 and SN74LS323 Are Similar But Have Synchronous Clear
  • Applications:
    • Stacked or Push-Down Registers Buffer Storage, and Accumulator Registers

 

These Schottky TTL eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both function-select lines, S0 and S1, high. This places the three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. A direct overriding input is provided to clear the register whether the outputs are enabled or off.

 

These Schottky TTL eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both function-select lines, S0 and S1, high. This places the three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. A direct overriding input is provided to clear the register whether the outputs are enabled or off.

 
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 8-Bit Universal Shift/Storage Registers 數(shù)據(jù)表 1988年 3月 1日

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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