SN54ABT823

正在供貨

具有三態(tài)輸出的 9 位總線接口觸發(fā)器

產(chǎn)品詳情

Number of channels 9 Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 48 IOH (max) (mA) -24 Supply current (max) (μA) 38000 Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 9 Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 48 IOH (max) (mA) -24 Supply current (max) (μA) 38000 Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
LCCC (FK) 28 130.6449 mm2 11.43 x 11.43
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Buffered Control Inputs to Reduce dc Loading Effects
  • Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK) and Flatpacks (W), and Standard Plastic (NT) and Ceramic (JT) DIPs

EPIC-IIB is a trademark of Texas Instruments Incorporated.
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Buffered Control Inputs to Reduce dc Loading Effects
  • Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK) and Flatpacks (W), and Standard Plastic (NT) and Ceramic (JT) DIPs

EPIC-IIB is a trademark of Texas Instruments Incorporated.

These 9-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

With the clock-enable (CLKEN\) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, thus latching the outputs. Taking the clear (CLR\) input low causes the nine Q outputs to go low, independently of the clock.

A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT823 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT823 is characterized for operation from -40°C to 85°C.

These 9-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

With the clock-enable (CLKEN\) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, thus latching the outputs. Taking the clear (CLR\) input low causes the nine Q outputs to go low, independently of the clock.

A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT823 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT823 is characterized for operation from -40°C to 85°C.

下載 觀看帶字幕的視頻 視頻

技術(shù)文檔

star =有關(guān)此產(chǎn)品的 TI 精選熱門文檔
未找到結(jié)果。請清除搜索并重試。
查看全部 23
類型 標題 下載最新的英語版本 日期
* 數(shù)據(jù)表 9-Bit Bus-Interface Flip-Flops With 3-State Outputs 數(shù)據(jù)表 (Rev. E) 1997年 5月 1日
* SMD SN54ABT823 SMD 5962-94508 2016年 6月 21日
應(yīng)用手冊 慢速或浮點 CMOS 輸入的影響 (Rev. E) PDF | HTML 英語版 (Rev.E) 2025年 3月 26日
應(yīng)用手冊 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
選擇指南 Logic Guide (Rev. AB) 2017年 6月 12日
應(yīng)用手冊 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語版本 (Rev.AC) PDF | HTML 2014年 11月 17日
選擇指南 《高級總線接口邏輯器件選擇指南》 英語版 2010年 7月 7日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
應(yīng)用手冊 選擇正確的電平轉(zhuǎn)換解決方案 (Rev. A) 英語版 (Rev.A) 2006年 3月 23日
應(yīng)用手冊 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
應(yīng)用手冊 Quad Flatpack No-Lead Logic Packages (Rev. D) 2004年 2月 16日
應(yīng)用手冊 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
應(yīng)用手冊 Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
應(yīng)用手冊 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
應(yīng)用手冊 Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) 1997年 6月 1日
應(yīng)用手冊 使用邏輯器件進行設(shè)計 (Rev. C) 1997年 6月 1日
應(yīng)用手冊 Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 1997年 3月 1日
應(yīng)用手冊 Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 1996年 12月 1日
應(yīng)用手冊 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
應(yīng)用手冊 Live Insertion 1996年 10月 1日
應(yīng)用手冊 Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日
選擇指南 Logic Guide (Rev. AC) PDF | HTML 1994年 6月 1日

設(shè)計和開發(fā)

如需其他信息或資源，請點擊以下任一標題進入詳情頁面查看（如有）。

封裝 引腳 CAD 符號、封裝和 3D 模型
LCCC (FK) 28 Ultra Librarian

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點
  • 封裝廠地點

支持和培訓(xùn)

視頻