DSD1792A
- Supports Both DSD and PCM Formats
- 24-Bit Resolution
- Analog Performance:
- Dynamic Range:
- 132 dB (9 V rms, Mono)
- 129 dB (4.5 V rms, Stereo)
- 127 dB (2 V rms, Stereo)
- THD+N: 0.0004%
- Dynamic Range:
- Differential Current Output: 7.8 mA p-p
- 8× Oversampling Digital Filter:
- Stop-Band Attenuation: –130 dB
- Pass-Band Ripple: ±0.00001 dB
- Sampling Frequency: 10 kHz to 200 kHz
- System Clock: 128, 192, 256, 384, 512, or 768 fS With Autodetect
- Accepts 16-, 20-, and 24-Bit Audio Data
- PCM Data Formats: Standard, I2S, and Left-Justified
- Optional Interface to External Digital Filter or DSP Available
- TDMCA Interface Available
- User-Programmable Mode Controls:
- Digital Attenuation: 0 dB to –120 dB, 0.5 dB/Step
- Digital De-Emphasis
- Digital Filter Rolloff: Sharp or Slow
- Soft Mute
- Dual Supply Operation:
- 5 V Analog, 3.3 V Digital
- 5-V Tolerant Digital Inputs
- Small 28-Lead SSOP Package
- APPLICATIONS
- A/V Receivers
- SACD Player
- DVD Players
- HDTV Receivers
- Car Audio Systems
- Digital Multi-Track Recorders
- Other Applications Requiring 24-Bit Audio
The DSD1792A is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TIs advanced-segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The DSD1792A provides balanced current outputs, allowing the user to optimize analog performance externally. The DSD1792A accepts the PCM and DSD audio data formats, providing easy interfacing to audio DSP and decoder chips. The DSD1792A also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through a 4-wire serial control port, which supports register write and readback functions. The DSD1792A also supports the time-division-multiplexed command and audio (TDMCA) data format.
技術(shù)文檔
| 類型 | 標(biāo)題 | 下載最新的英語版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數(shù)據(jù)表 | 24-Bit, 192-kHz Sampling, Advanced Segment, Audio Stereo DAC 數(shù)據(jù)表 (Rev. B) | 2006年 11月 30日 |
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| 封裝 | 引腳 | CAD 符號(hào)、封裝和 3D 模型 |
|---|---|---|
| SSOP (DB) | 28 | Ultra Librarian |
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