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DS90C385A

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LVDS 發(fā)送器平板顯示器 (85MHz)

產(chǎn)品詳情

Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 56 113.4 mm2 14 x 8.1
  • Pin-to-Pin Compatible to DS90C383, DS90C383A and DS90C385
  • No Special Start-Up Sequence Required between Clock/Data and /PD Pins. Input Signals (Clock and Data) can be Applied Either Before or After the Device is Powered.
  • Support Spread Spectrum Clocking up to 100kHz Frequency Modulation and Deviations of ±2.5% Center Spread or -5% Down Spread
  • “Input Clock Detection" Feature Will Pull All LVDS Pairs to Logic Low When Input Clock is Missing and When /PD Pin is Logic High
  • 18 to 87.5 MHz Shift Clock Support
  • Tx Power Consumption < 147 mW (typ) at 87.5MHz Grayscale
  • Tx Power-Down Mode < 60 μW (typ)
  • Supports VGA, SVGA, XGA, SXGA(Dual Pixel), SXGA+(Dual Pixel), UXGA(Dual Pixel).
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 2.45 Gbps Throughput
  • Up to 306.25Megabyte/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires No External Components
  • Compliant to TIA/EIA-644 LVDS standard
  • Low Profile 56-lead TSSOP Package

All trademarks are the property of their respective owners.

  • Pin-to-Pin Compatible to DS90C383, DS90C383A and DS90C385
  • No Special Start-Up Sequence Required between Clock/Data and /PD Pins. Input Signals (Clock and Data) can be Applied Either Before or After the Device is Powered.
  • Support Spread Spectrum Clocking up to 100kHz Frequency Modulation and Deviations of ±2.5% Center Spread or -5% Down Spread
  • “Input Clock Detection" Feature Will Pull All LVDS Pairs to Logic Low When Input Clock is Missing and When /PD Pin is Logic High
  • 18 to 87.5 MHz Shift Clock Support
  • Tx Power Consumption < 147 mW (typ) at 87.5MHz Grayscale
  • Tx Power-Down Mode < 60 μW (typ)
  • Supports VGA, SVGA, XGA, SXGA(Dual Pixel), SXGA+(Dual Pixel), UXGA(Dual Pixel).
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 2.45 Gbps Throughput
  • Up to 306.25Megabyte/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires No External Components
  • Compliant to TIA/EIA-644 LVDS standard
  • Low Profile 56-lead TSSOP Package

All trademarks are the property of their respective owners.

The DS90C385A is a pin to pin compatible replacement for DS90C383, DS90C383A and DS90C385. The DS90C385A has additional features and improvements making it an ideal replacement for DS90C383, DS90C383A and DS90C385. family of LVDS Transmitters.

The DS90C385A transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over the fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 87.5 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 612.5Mbps per LVDS data channel. Using a 87.5 MHz clock, the data throughput is 306.25Mbytes/sec. This transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe FPDLink Receiver without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces with added Spread Spectrum Clocking support.

The DS90C385A is a pin to pin compatible replacement for DS90C383, DS90C383A and DS90C385. The DS90C385A has additional features and improvements making it an ideal replacement for DS90C383, DS90C383A and DS90C385. family of LVDS Transmitters.

The DS90C385A transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over the fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 87.5 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 612.5Mbps per LVDS data channel. Using a 87.5 MHz clock, the data throughput is 306.25Mbytes/sec. This transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe FPDLink Receiver without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces with added Spread Spectrum Clocking support.

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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 DS90C385A 3.3V Prog LVDS Trans 24-Bit FPD Link-87.5 MHz 數(shù)據(jù)表 (Rev. K) 2013年 4月 17日
應(yīng)用手冊 High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 2018年 11月 9日
應(yīng)用手冊 How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 2018年 6月 29日
應(yīng)用手冊 AN-1032 An Introduction to FPD-Link (Rev. C) 2017年 8月 8日
用戶指南 FLINK3V8BT-85 Evaluation Kit (Rev. A) 2016年 8月 24日
應(yīng)用手冊 Receiver Skew Margin for Channel Link I and FPD Link I Devices 2016年 1月 13日
應(yīng)用手冊 TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 2004年 5月 15日
應(yīng)用手冊 AN-1056 STN Application Using FPD-Link 2004年 5月 14日
應(yīng)用手冊 AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 2004年 5月 14日

設(shè)計(jì)和開發(fā)

如需其他信息或資源,請點(diǎn)擊以下任一標(biāo)題進(jìn)入詳情頁面查看(如有)。

評估板

FLINK3V8BT-85 — 用于 FPD 鏈接系列串行器和解串器 LVDS 器件的評估套件

FPD-Link evaluation kit contains a Transmitter (Tx) board, a Receiver (Rx) board along with interfacing cables. This kit will demonstrate the chipsets interfacing from test equipment or a graphics controller using Low Voltage Differential Signaling (LVDS) to a receiver board.

The Transmitter board (...)

用戶指南: PDF
TI.com 上無現(xiàn)貨
仿真模型

DS90C385A IBIS Model

SNLM080.ZIP (7 KB) - IBIS Model
模擬工具

PSPICE-FOR-TI — PSpice? for TI 設(shè)計(jì)和仿真工具

PSpice? for TI 可提供幫助評估模擬電路功能的設(shè)計(jì)和仿真環(huán)境。此功能齊全的設(shè)計(jì)和仿真套件使用 Cadence? 的模擬分析引擎。PSpice for TI 可免費(fèi)使用,包括業(yè)內(nèi)超大的模型庫之一,涵蓋我們的模擬和電源產(chǎn)品系列以及精選的模擬行為模型。

借助?PSpice for TI 的設(shè)計(jì)和仿真環(huán)境及其內(nèi)置的模型庫,您可對復(fù)雜的混合信號設(shè)計(jì)進(jìn)行仿真。創(chuàng)建完整的終端設(shè)備設(shè)計(jì)和原型解決方案,然后再進(jìn)行布局和制造,可縮短產(chǎn)品上市時(shí)間并降低開發(fā)成本。?

在?PSpice for TI 設(shè)計(jì)和仿真工具中,您可以搜索 TI (...)
模擬工具

TINA-TI — 基于 SPICE 的模擬仿真程序

TINA-TI 提供了 SPICE 所有的傳統(tǒng)直流、瞬態(tài)和頻域分析以及更多。TINA 具有廣泛的后處理功能,允許您按照希望的方式設(shè)置結(jié)果的格式。虛擬儀器允許您選擇輸入波形、探針電路節(jié)點(diǎn)電壓和波形。TINA 的原理圖捕獲非常直觀 - 真正的“快速入門”。

TINA-TI 安裝需要大約 500MB。直接安裝,如果想卸載也很容易。我們相信您肯定會愛不釋手。

TINA 是德州儀器 (TI) 專有的 DesignSoft 產(chǎn)品。該免費(fèi)版本具有完整的功能,但不支持完整版 TINA 所提供的某些其他功能。

如需獲取可用 TINA-TI 模型的完整列表,請參閱:SpiceRack - 完整列表 

需要 HSpice (...)

用戶指南: PDF
英語版 (Rev.A): PDF
參考設(shè)計(jì)

TIDA-010013 — 適用于 Sitara? 處理器的 RGB 到 OLDI/LVDS 顯示橋參考設(shè)計(jì)

市場對更高分辨率顯示器的需求一直在不斷增加。這需要采用更高像素的時(shí)鐘,可能會產(chǎn)生高 EMI 發(fā)射和高防噪性能等設(shè)計(jì)難題。因此,視頻接口現(xiàn)在已從傳統(tǒng)的 RGB 過渡到 LVDS 視頻接口。由于集成圖形單元的微處理器可以僅輸出單端 RGB 視頻數(shù)據(jù),本參考設(shè)計(jì)展示如何輕松地將 RGB 轉(zhuǎn)換為 LVDS。
設(shè)計(jì)指南: PDF
原理圖: PDF
封裝 引腳 CAD 符號、封裝和 3D 模型
TSSOP (DGG) 56 Ultra Librarian

訂購和質(zhì)量

包含信息:
  • RoHS
  • REACH
  • 器件標(biāo)識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息:
  • 制造廠地點(diǎn)
  • 封裝廠地點(diǎn)

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