產(chǎn)品詳情

Resolution (Bits) 10 Number of DAC channels 1 Interface type Parallel CMOS Sample/update rate (Msps) 200 Features Low Power Rating Catalog Interpolation 1x Power consumption (typ) (mW) 170 SFDR (dB) 76 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Ext, Int
Resolution (Bits) 10 Number of DAC channels 1 Interface type Parallel CMOS Sample/update rate (Msps) 200 Features Low Power Rating Catalog Interpolation 1x Power consumption (typ) (mW) 170 SFDR (dB) 76 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Ext, Int
SOIC (DW) 28 184.37 mm2 17.9 x 10.3 TSSOP (PW) 28 62.08 mm2 9.7 x 6.4
  • SINGLE +5V OR +3V OPERATION
  • HIGH SFDR: 5MHz Output at 100MSPS: 68dBc
  • LOW GLITCH: 3pV-s
  • LOW POWER: 170mW at +5V
  • INTERNAL REFERENCE:
         Optional Ext. Reference
         Adjustable Full-Scale Range
         Multiplying Option
  • APPLICATIONS
    • COMMUNICATION TRANSMIT CHANNELS
           WLL, Cellular Base Station
           Digital Microwave Links
           Cable Modems
    • WAVEFORM GENERATION
           Direct Digital Synthesis (DDS)
           Arbitrary Waveform Generation (ARB)
    • MEDICAL/ULTRASOUND
    • HIGH-SPEED INSTRUMENTATION AND CONTROL
    • VIDEO, DIGITAL TV
  • SINGLE +5V OR +3V OPERATION
  • HIGH SFDR: 5MHz Output at 100MSPS: 68dBc
  • LOW GLITCH: 3pV-s
  • LOW POWER: 170mW at +5V
  • INTERNAL REFERENCE:
         Optional Ext. Reference
         Adjustable Full-Scale Range
         Multiplying Option
  • APPLICATIONS
    • COMMUNICATION TRANSMIT CHANNELS
           WLL, Cellular Base Station
           Digital Microwave Links
           Cable Modems
    • WAVEFORM GENERATION
           Direct Digital Synthesis (DDS)
           Arbitrary Waveform Generation (ARB)
    • MEDICAL/ULTRASOUND
    • HIGH-SPEED INSTRUMENTATION AND CONTROL
    • VIDEO, DIGITAL TV

The DAC900 is a high-speed, Digital-to-Analog Converter (DAC) offering a 10-bit resolution option within the SpeedPlus family of high-performance converters. Featuring pin compatibility among family members, the DAC908, DAC902, and DAC904 provide a component selection option to an 8-, 12-, and 14-bit resolution, respectively. All models within this family of DACs support update rates in excess of 165MSPS with excellent dynamic performance,and are especially suited to fulfill the demands of a variety of applications.

The advanced segmentation architecture of the DAC900 is optimized to provide a high Spurious-Free Dynamic Range (SFDR) for single-tone, as well as for multi-tone signals—essential when used for the transmit signal path of communication systems.

The DAC900 has a high impedance (200k) current output with a nominal range of 20mA and an output compliance of up to 1.25V. The differential outputs allow for both a differential or single-ended analog signal interface. The close matching of the current outputs ensures superior dynamic performance in the differential configuration, which can be implemented with a transformer.

Utilizing a small geometry CMOS process, the monolithic DAC900 can be operated on a wide, single-supply range of +2.7V to +5.5V. Its low power consumption allows for use in portable and battery-operated systems. Further optimization can be realized by lowering the output current with the adjustable full-scale option.

For noncontinuous operation of the DAC900, a power-down mode results in only 45mW of standby power.

The DAC900 comes with an integrated 1.24V bandgap reference and edge-triggered input latches, offering a complete converter solution. Both +3V and +5V CMOS logic families can be interfaced to the DAC900.

The reference structure of the DAC900 allows for additional flexibility by utilizing the on-chip reference, or applying an external reference. The full-scale output current can be adjusted over a span of 2mA to 20mA, with one external resistor, while maintaining the specified dynamic performance.

The DAC900 is available in SO-28 and TSSOP-28 packages.

The DAC900 is a high-speed, Digital-to-Analog Converter (DAC) offering a 10-bit resolution option within the SpeedPlus family of high-performance converters. Featuring pin compatibility among family members, the DAC908, DAC902, and DAC904 provide a component selection option to an 8-, 12-, and 14-bit resolution, respectively. All models within this family of DACs support update rates in excess of 165MSPS with excellent dynamic performance,and are especially suited to fulfill the demands of a variety of applications.

The advanced segmentation architecture of the DAC900 is optimized to provide a high Spurious-Free Dynamic Range (SFDR) for single-tone, as well as for multi-tone signals—essential when used for the transmit signal path of communication systems.

The DAC900 has a high impedance (200k) current output with a nominal range of 20mA and an output compliance of up to 1.25V. The differential outputs allow for both a differential or single-ended analog signal interface. The close matching of the current outputs ensures superior dynamic performance in the differential configuration, which can be implemented with a transformer.

Utilizing a small geometry CMOS process, the monolithic DAC900 can be operated on a wide, single-supply range of +2.7V to +5.5V. Its low power consumption allows for use in portable and battery-operated systems. Further optimization can be realized by lowering the output current with the adjustable full-scale option.

For noncontinuous operation of the DAC900, a power-down mode results in only 45mW of standby power.

The DAC900 comes with an integrated 1.24V bandgap reference and edge-triggered input latches, offering a complete converter solution. Both +3V and +5V CMOS logic families can be interfaced to the DAC900.

The reference structure of the DAC900 allows for additional flexibility by utilizing the on-chip reference, or applying an external reference. The full-scale output current can be adjusted over a span of 2mA to 20mA, with one external resistor, while maintaining the specified dynamic performance.

The DAC900 is available in SO-28 and TSSOP-28 packages.
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類型 標題 下載最新的英語版本 日期
* 數(shù)據(jù)表 DAC900 10-Bit 165-MSPS Digital-to-Analog Converter 數(shù)據(jù)表 (Rev. B) 2002年 5月 29日
EVM 用戶指南 DAC90x Evaluation Module User's Guide 2017年 8月 8日
應(yīng)用手冊 Wideband Complementary Current Output DAC Single-Ended Interface (Rev. A) 2015年 5月 8日
應(yīng)用手冊 High Speed, Digital-to-Analog Converters Basics (Rev. A) 2012年 10月 23日
應(yīng)用手冊 所選封裝材料的熱學和電學性質(zhì) 2008年 10月 16日
應(yīng)用手冊 高速數(shù)據(jù)轉(zhuǎn)換 英語版 2008年 10月 16日
用戶指南 DEM-DAC90x: Evaluation Fixture for the DAC900, DAC902, DAC904, DAC908 2000年 9月 27日

設(shè)計和開發(fā)

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評估板

DAC900EVM — DAC900 10 位 165-MSPS 模數(shù)轉(zhuǎn)換器 (DAC) 評估模塊

DAC900 評估模塊 (EVM) 旨在評估 10 位、高速、
CMOS 接口 DAC900。該 EVM 只需極少的簡單外部組件，更大限度地降低了系統(tǒng)成本和功耗。
用戶指南: PDF
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仿真模型

DAC900 IBIS Model for 3.3V

SLWC072.ZIP (6 KB) - IBIS Model
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仿真模型

DAC900 IBIS Model for 5V

SLWC073.ZIP (5 KB) - IBIS Model
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計算工具

MATCHGAIN-CALC — 寬帶輔助電流輸出 DAC 轉(zhuǎn) SE 接口：增益和合規(guī)電壓擺幅的改進匹配

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光繪文件

DAC900 Design File

SBAC225.ZIP (1677 KB)
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模擬工具

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封裝 引腳 CAD 符號、封裝和 3D 模型
SOIC (DW) 28 Ultra Librarian
TSSOP (PW) 28 Ultra Librarian

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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