CY74FCT374T

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具有三態(tài)輸出的八路 D 類寄存器

產(chǎn)品詳情

Number of channels 8 Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type TTL, TTL-Compatible CMOS Output type 3-State, CMOS Clock frequency (max) (MHz) 100 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (μA) 200 Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 8 Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type TTL, TTL-Compatible CMOS Output type 3-State, CMOS Clock frequency (max) (MHz) 100 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (μA) 200 Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
PDIP (N) 20 228.702 mm2 24.33 x 9.4 SOIC (DW) 20 131.84 mm2 12.8 x 10.3 SSOP (DBQ) 20 51.9 mm2 8.65 x 6
  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Edge-Triggered D-Type Inputs
  • 250-MHz Typical Switching Rate
  • CY54FCT374T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT374T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current
  • 3-State Outputs
  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Edge-Triggered D-Type Inputs
  • 250-MHz Typical Switching Rate
  • CY54FCT374T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT374T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current
  • 3-State Outputs

The \x92FCT374T devices are high-speed, low-power, octal D-type flip-flops, featuring separate D-type inputs for each flip-flop. These devices have 3-state outputs for bus-oriented applications. A buffered clock (CP) and output-enable (OE\) inputs are common to all flip-flops. The eight flip-flops in the \x92FCT374T store the state of their individual D inputs that meet the setup-time and hold-time requirements on the low-to-high CP transition. When OE\ is low, the contents of the eight flip-flops are available at the outputs. When OE\ is high, the outputs are in the high-impedance state. The state of OE\ does not affect the state of the flip-flops.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT374T devices are high-speed, low-power, octal D-type flip-flops, featuring separate D-type inputs for each flip-flop. These devices have 3-state outputs for bus-oriented applications. A buffered clock (CP) and output-enable (OE\) inputs are common to all flip-flops. The eight flip-flops in the \x92FCT374T store the state of their individual D inputs that meet the setup-time and hold-time requirements on the low-to-high CP transition. When OE\ is low, the contents of the eight flip-flops are available at the outputs. When OE\ is high, the outputs are in the high-impedance state. The state of OE\ does not affect the state of the flip-flops.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 8-Bit Registers With 3-State Outputs 數(shù)據(jù)表 (Rev. A) 2001年 10月 1日
應(yīng)用手冊 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
選擇指南 Logic Guide (Rev. AB) 2017年 6月 12日
應(yīng)用手冊 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語版本 (Rev.AC) PDF | HTML 2014年 11月 17日
選擇指南 《高級總線接口邏輯器件選擇指南》 英語版 2010年 7月 7日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
應(yīng)用手冊 選擇正確的電平轉(zhuǎn)換解決方案 (Rev. A) 英語版 (Rev.A) 2006年 3月 23日
應(yīng)用手冊 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用戶指南 CYFCT Parameter Measurement Information 2001年 4月 2日
選擇指南 Logic Guide (Rev. AC) PDF | HTML 1994年 6月 1日

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評估板

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14-24-LOGIC-EVM 評估模塊 (EVM) 設(shè)計用于支持采用 14 引腳至 24 引腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯器件。

用戶指南: PDF | HTML
英語版 (Rev.B): PDF | HTML
TI.com 上無現(xiàn)貨
封裝 引腳 CAD 符號、封裝和 3D 模型
PDIP (N) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian
SSOP (DBQ) 20 Ultra Librarian

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點(diǎn)
  • 封裝廠地點(diǎn)

支持和培訓(xùn)

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