CY54FCT841T

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具有三態(tài)輸出的 10 位總線接口 D 類鎖存器

產(chǎn)品詳情

Technology family FCT Operating temperature range (°C) -55 to 125 Rating Military
Technology family FCT Operating temperature range (°C) -55 to 125 Rating Military
CDIP (JT) 24 221.44 mm2 32 x 6.92
  • Function, Pinout, and Drive Compatible With FCT, F, and AM29841 Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Fully Compatible With TTL Input and Output Logic Levels
  • High-Speed Parallel Latches
  • Buffered Common Latch-Enable Input
  • 3-State Outputs
  • CY54FCT841T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT841T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current
  • Function, Pinout, and Drive Compatible With FCT, F, and AM29841 Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Fully Compatible With TTL Input and Output Logic Levels
  • High-Speed Parallel Latches
  • Buffered Common Latch-Enable Input
  • 3-State Outputs
  • CY54FCT841T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT841T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current

The \x92FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The \x92FCT841T devices are buffered 10-bit-wide versions of the FCT373 function.

The \x92FCT841T devices\x92 high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The \x92FCT841T devices are buffered 10-bit-wide versions of the FCT373 function.

The \x92FCT841T devices\x92 high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 10-Bit Latches With 3-State Outputs 數(shù)據(jù)表 (Rev. A) 2001年 10月 1日

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識(shí)
  • 引腳鍍層/焊球材料
  • MSL 等級(jí)/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測(cè)
包含信息：
  • 制造廠地點(diǎn)
  • 封裝廠地點(diǎn)

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