CY54FCT574T
- Function, Pinout, and Drive Compatible With FCT and F Logic
- Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
- Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
- Ioff Supports Partial-Power-Down Mode Operation
- Matched Rise and Fall Times
- Fully Compatible With TTL Input and Output Logic Levels
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Edge-Triggered D-Type Inputs
- 250-MHz Typical Switching Rate
- CY54FCT574T
- 32-mA Output Sink Current
- 12-mA Output Source Current
- CY74FCT574T
- 64-mA Output Sink Current
- 32-mA Output Source Current
- 3-State Outputs
The \x92FCT574T devices are high-speed, low-power, octal D-type flip-flops, featuring separate D-type inputs for each flip-flop. These devices have 3-state outputs for bus-oriented applications. A buffered clock (CP) and output-enable (OE\) inputs are common to all flip-flops. The \x92FCT574T are identical to \x92FCT374T, except for a flow-through pinout to simplify board design. The eight flip-flops in the \x92FCT574T store the state of their individual D inputs that meet the setup-time and hold-time requirements on the low-to-high CP transition. When OE\ is low, the contents of the eight flip-flops are available at the outputs. When OE\ is high, the outputs are in the high-impedance state. The state of OE\ does not affect the state of the flip-flops.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
技術(shù)文檔
| 類型 | 標(biāo)題 | 下載最新的英語(yǔ)版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數(shù)據(jù)表 | 8-Bit Registers With 3-State Outputs 數(shù)據(jù)表 | 2001年 10月 11日 |
訂購(gòu)和質(zhì)量
- RoHS
- REACH
- 器件標(biāo)識(shí)
- 引腳鍍層/焊球材料
- MSL 等級(jí)/回流焊峰值溫度
- MTBF/時(shí)基故障估算
- 材料成分
- 鑒定摘要
- 持續(xù)可靠性監(jiān)測(cè)
- 制造廠地點(diǎn)
- 封裝廠地點(diǎn)