CD74HC195

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高速 CMOS 邏輯 4 位并行訪問寄存器

產(chǎn)品詳情

Configuration Universal Bits (#) 4 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 60 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (μA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Catalog
Configuration Universal Bits (#) 4 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 60 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (μA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Catalog
PDIP (N) 16 181.42 mm2 19.3 x 9.4 SOIC (D) 16 59.4 mm2 9.9 x 6 SOP (NS) 16 79.56 mm2 10.2 x 7.8 TSSOP (PW) 16 32 mm2 5 x 6.4
  • Asynchronous Master Reset
  • J, K\,(D) Inputs to First Stage
  • Fully Synchronous Serial or Parallel Data Transfer
  • Shift Right and Parallel Load Capability
  • Complementary Output From Last Stage
  • Buffered Inputs
  • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V

Data sheet acquired from Harris Semiconductor
  • Asynchronous Master Reset
  • J, K\,(D) Inputs to First Stage
  • Fully Synchronous Serial or Parallel Data Transfer
  • Shift Right and Parallel Load Capability
  • Complementary Output From Last Stage
  • Buffered Inputs
  • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V

Data sheet acquired from Harris Semiconductor

The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds.

The two modes of operation, shift right (Q0-Q1) and parallel load, are controlled by the state of the Parallel Enable (PE)\ input. Serial data enters the first flip-flop (Q0) via the J and K\ inputs when the PE\ input is high, and is shifted one bit in the direction Q0-Q1-Q2-Q3 following each Low to High clock transition. The J and K\ inputs provide the flexibility of the JK-type input for special applications and by tying the two pins together, the simple D-type input for general applications. The device appears as four common-clocked D flip-flops when the PE\ input is Low. After the Low to High clock transition, data on the parallel inputs (D0-D3) is transferred to the respective Q0-Q3 outputs. Shift left operation (Q3-Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE\ input low.

All parallel and serial data transfers are synchronous, occurring after each Low to High clock transition. The ’HC195 series utilizes edge triggering; therefore, there is no restriction on the activity of the J, K\, Pn and PE\ inputs for logic operations, other than set-up and hold time requirements. A Low on the asynchronous Master Reset (MR)\ input sets all Q outputs Low, independent of any other input condition.

The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds.

The two modes of operation, shift right (Q0-Q1) and parallel load, are controlled by the state of the Parallel Enable (PE)\ input. Serial data enters the first flip-flop (Q0) via the J and K\ inputs when the PE\ input is high, and is shifted one bit in the direction Q0-Q1-Q2-Q3 following each Low to High clock transition. The J and K\ inputs provide the flexibility of the JK-type input for special applications and by tying the two pins together, the simple D-type input for general applications. The device appears as four common-clocked D flip-flops when the PE\ input is Low. After the Low to High clock transition, data on the parallel inputs (D0-D3) is transferred to the respective Q0-Q3 outputs. Shift left operation (Q3-Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE\ input low.

All parallel and serial data transfers are synchronous, occurring after each Low to High clock transition. The ’HC195 series utilizes edge triggering; therefore, there is no restriction on the activity of the J, K\, Pn and PE\ inputs for logic operations, other than set-up and hold time requirements. A Low on the asynchronous Master Reset (MR)\ input sets all Q outputs Low, independent of any other input condition.
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 CD54HC195, CD74HC195 數(shù)據(jù)表 (Rev. E) 2003年 10月 21日

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識(shí)
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點(diǎn)
  • 封裝廠地點(diǎn)

支持和培訓(xùn)