CD4094B
- 3-state parallel outputs for connection to common bus
- Separate serial outputs synchronous to both positive and negative clock edges for cascading
- Medium speed operation - 5 MHz at 10 V (typ.)
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package temperature range):
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V - 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications
- Serial-to-parallel data conversion
- Remote control holding register
- Dual-rank shift, hold, and bus applications
CD4094B is an 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the STROBE input is high. Data in the storage register appears at the outputs whenever the OUTPUT-ENABLE signal is high.
Two serial outputs are available for cascading a number of CD4094B devices. Data is available at the QS serial output terminal on positive clock edges to allow for high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information, available at the Q'S terminal on the next negative clock edge, provides a means for cascading CD4094B devices when the clock rise time is slow.
The CD4094B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
技術(shù)文檔
| 類型 | 標(biāo)題 | 下載最新的英語版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數(shù)據(jù)表 | CD4094B 數(shù)據(jù)表 (Rev. B) | 2003年 6月 27日 | |||
| 應(yīng)用手冊(cè) | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022年 12月 15日 | |||
| 選擇指南 | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||||
| 應(yīng)用手冊(cè) | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||||
| 選擇指南 | 邏輯器件指南 2014 (Rev. AA) | 最新英語版本 (Rev.AC) | PDF | HTML | 2014年 11月 17日 | ||
| 用戶指南 | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||||
| 應(yīng)用手冊(cè) | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||||
| 用戶指南 | Signal Switch Data Book (Rev. A) | 2003年 11月 14日 | ||||
| 應(yīng)用手冊(cè) | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | 2001年 12月 3日 | ||||
| 選擇指南 | Logic Guide (Rev. AC) | PDF | HTML | 1994年 6月 1日 |
設(shè)計(jì)和開發(fā)
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14-24-LOGIC-EVM — 采用 14 引腳至 24 引腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產(chǎn)品通用評(píng)估模塊
14-24-LOGIC-EVM 評(píng)估模塊 (EVM) 設(shè)計(jì)用于支持采用 14 引腳至 24 引腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯器件。
| 封裝 | 引腳 | CAD 符號(hào)、封裝和 3D 模型 |
|---|---|---|
| PDIP (N) | 16 | Ultra Librarian |
| SOP (NS) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
訂購和質(zhì)量
- RoHS
- REACH
- 器件標(biāo)識(shí)
- 引腳鍍層/焊球材料
- MSL 等級(jí)/回流焊峰值溫度
- MTBF/時(shí)基故障估算
- 材料成分
- 鑒定摘要
- 持續(xù)可靠性監(jiān)測(cè)
- 制造廠地點(diǎn)
- 封裝廠地點(diǎn)