CD4017B
- Fully static operation
- Medium speed operation…10 MHz (typ.) at VDD = 10 V
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Decade counter/decimal decode display (CD4017B)
- Binary counter/decoder
- Frequency division
- Counter control/timers
- Divde-by-N counting
- For further application information, see ICAN-6166 "COS/MOS MSI Counter and Register Design and Applications"
CD4017B and CD4022B are 5-stage and 4-stage Johnson counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times.
These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT siganl is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY-OUT signal completes on cycle every 10 clock input cycles in the CD4017B or every 8 clock input cycles in the CD4022B and is used to ripple-clock the succeeding device in a multi-device counting chain.
The CD4017B and CD4022B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD4017B types also are supplied in 16-lead small-outline packages (M and M96 suffixes).
技術文檔
| 類型 | 標題 | 下載最新的英語版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數據表 | CD4017B, CD4022B TYPES 數據表 (Rev. C) | 2004年 2月 17日 | |||
| 選擇指南 | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||||
| 應用手冊 | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||||
| 選擇指南 | 邏輯器件指南 2014 (Rev. AA) | 最新英語版本 (Rev.AC) | PDF | HTML | 2014年 11月 17日 | ||
| 用戶指南 | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||||
| 應用手冊 | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||||
| 用戶指南 | Signal Switch Data Book (Rev. A) | 2003年 11月 14日 | ||||
| 應用手冊 | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | 2001年 12月 3日 | ||||
| 選擇指南 | Logic Guide (Rev. AC) | PDF | HTML | 1994年 6月 1日 |
設計和開發(fā)
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14-24-LOGIC-EVM — 采用 14 引腳至 24 引腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模塊
14-24-LOGIC-EVM 評估模塊 (EVM) 設計用于支持采用 14 引腳至 24 引腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯器件。
TIDA-00223 — 車用音頻 I2S 同軸 D 類放大器的參考設計
| 封裝 | 引腳 | CAD 符號、封裝和 3D 模型 |
|---|---|---|
| PDIP (N) | 16 | Ultra Librarian |
| SOIC (D) | 16 | Ultra Librarian |
| SOP (NS) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
訂購和質量
- RoHS
- REACH
- 器件標識
- 引腳鍍層/焊球材料
- MSL 等級/回流焊峰值溫度
- MTBF/時基故障估算
- 材料成分
- 鑒定摘要
- 持續(xù)可靠性監(jiān)測
- 制造廠地點
- 封裝廠地點