CD4013B

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CMOS 雙通道 D 類觸發(fā)器

產品詳情

Number of channels 2 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 24 IOL (max) (mA) 6.8 IOH (max) (mA) -6.8 Supply current (max) (μA) 600 Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog
Number of channels 2 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 24 IOL (max) (mA) 6.8 IOH (max) (mA) -6.8 Supply current (max) (μA) 600 Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog
PDIP (N) 14 181.42 mm2 19.3 x 9.4 SOIC (D) 14 51.9 mm2 8.65 x 6 SOP (NS) 14 79.56 mm2 10.2 x 7.8 TSSOP (PW) 14 32 mm2 5 x 6.4
  • Asynchronous Set-Reset Capability
  • Static Flip-Flop Operation
  • Medium-Speed Operation: 16 MHz (Typical) Clock Toggle Rate at 10-V Supply
  • Standardized Symmetrical Output Characteristics
  • Maximum Input Current Of 1-μA at 18 V Over Full Package Temperature Range:
    • 100 nA at 18 V and 25°C
  • Noise Margin (Over Full Package Temperature Range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Asynchronous Set-Reset Capability
  • Static Flip-Flop Operation
  • Medium-Speed Operation: 16 MHz (Typical) Clock Toggle Rate at 10-V Supply
  • Standardized Symmetrical Output Characteristics
  • Maximum Input Current Of 1-μA at 18 V Over Full Package Temperature Range:
    • 100 nA at 18 V and 25°C
  • Noise Margin (Over Full Package Temperature Range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V

The CD4013B device consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively.

The CD4013B types are supplied in 14-pin dual-in-line plastic packages (E suffix), 14-pin small-outline packages (M, MT, M96, and NSR suffixes), and 14-pin thin shrink small-outline packages (PW and PWR suffixes).

The CD4013B device consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively.

The CD4013B types are supplied in 14-pin dual-in-line plastic packages (E suffix), 14-pin small-outline packages (M, MT, M96, and NSR suffixes), and 14-pin thin shrink small-outline packages (PW and PWR suffixes).
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類型 標題 下載最新的英語版本 日期
* 數據表 CD4013B CMOS Dual D-Type Flip-Flop 數據表 (Rev. E) PDF | HTML 2016年 9月 30日
應用手冊 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
選擇指南 Logic Guide (Rev. AB) 2017年 6月 12日
應用手冊 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語版本 (Rev.AC) PDF | HTML 2014年 11月 17日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
應用手冊 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用戶指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
應用手冊 Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001年 12月 3日
選擇指南 Logic Guide (Rev. AC) PDF | HTML 1994年 6月 1日

設計和開發(fā)

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評估板

14-24-LOGIC-EVM — 采用 14 引腳至 24 引腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模塊

14-24-LOGIC-EVM 評估模塊 (EVM) 設計用于支持采用 14 引腳至 24 引腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯器件。

用戶指南: PDF | HTML
英語版 (Rev.B): PDF | HTML
TI.com 上無現貨
封裝 引腳 CAD 符號、封裝和 3D 模型
PDIP (N) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點
  • 封裝廠地點

支持和培訓

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