74AC11074

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具有清零和預(yù)設(shè)功能的雙通道上升沿觸發(fā) D 類觸發(fā)器

產(chǎn)品詳情

Number of channels 2 Technology family AC Supply voltage (min) (V) 3 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 125 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (μA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 2 Technology family AC Supply voltage (min) (V) 3 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 125 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (μA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 85 Rating Catalog
PDIP (N) 14 181.42 mm2 19.3 x 9.4 SOIC (D) 14 51.9 mm2 8.65 x 6 TSSOP (PW) 14 32 mm2 5 x 6.4
  • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)

 

EPIC is a trademark of Texas Instruments Incorporated.
  • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)

 

EPIC is a trademark of Texas Instruments Incorporated.

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The 74AC11074 is characterized for operation from -40°C to 85°C.

 

 

 

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The 74AC11074 is characterized for operation from -40°C to 85°C.

 

 

 
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SN74AC74 正在供貨 具有清零和預(yù)設(shè)功能的雙路正邊沿 D 類觸發(fā)器 Larger voltage range (2V to 6V)

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類型 標(biāo)題 下載最新的英語(yǔ)版本 日期
* 數(shù)據(jù)表 Dual D-Type Positive-Edge-Triggered Flip-Flop With Clear And Preset 數(shù)據(jù)表 (Rev. A) 1996年 4月 1日

訂購(gòu)和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識(shí)
  • 引腳鍍層/焊球材料
  • MSL 等級(jí)/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測(cè)
包含信息：
  • 制造廠地點(diǎn)
  • 封裝廠地點(diǎn)

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