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SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678

5.2.1 KeyStone I TCI661x, C6670, C665x devices

Table 5-3 shows the mapping of queues to high priority accumulation channels to DSP and function for TCI661x (16, 18, 14), C6670 and C665x devices. Note that each queue and event maps to a specific DSP core. Also, the queues shown are the suggested mapping. Other queues may be used. The channel to event mapping is fixed.

Table 5-3 High Priority Queue Mapping (TCI661x, C6670 C665x)

DSP	Queue	High Priority Channel	Interrupt Name	DSP Event
core N (N = 0 to 3)	704 + N	N	qmss_intr1_0+N	48
	708 + N	N + 4	qmss_intr1_4+N	49
	712 + N	N + 8	qmss_intr1_8+N	50
	716 + N	N + 12	qmss_intr1_12+N	51
	720 + N	N + 16	qmss_intr1_16+N	52
	724 + N	N + 20	qmss_intr1_20+N	53
	728 + N	N + 24	qmss_intr1_24+N	54
	732 + N	N + 28	qmss_intr1_28+N	55

The C665x devices have 1 or 2 DSPs, so Table 5-3 shows the mapping of queues to high priority accumulation channels where N=0 or 1, which maps only half of the high priority channels. Table 5-4 shows the mapping of the remaining channels, which, in effect, doubles interrupts to each core.

Table 5-4 High Priority Queue Mapping (C665x part 2)

DSP	Queue	High Priority Channel	Interrupt Name	DSP Event
core N (N = 0 to 1)	706 + N	N + 2	qmss_intr1_2+N	102
	710 + N	N + 6	qmss_intr1_6+N	103
	714 + N	N + 10	qmss_intr1_10+N	104
	718 + N	N + 14	qmss_intr1_14+N	105
	722 + N	N + 18	qmss_intr1_18+N	106
	726 + N	N + 22	qmss_intr1_22+N	107
	730 + N	N + 26	qmss_intr1_26+N	108
	734 + N	N + 30	qmss_intr1_30+N	109

Table 5-5 shows the mapping of queues to low priority accumulation channels. All low priority interrupts map to all DSPs. Also, the queues shown are the suggested mapping. Other queues may be used. The channel to event mapping is fixed.

Table 5-5 Low Priority Queue Mapping

Queues	Low Priority Channel	Interrupt Name	DSP Event
0 to 31	0	qmss_intr0_0	32
32 to 63	1	qmss_intr0_1	33
64 to 95	2	qmss_intr0_2	34
. . .	. . .	. . .	. . .
448 to 479	14	qmss_intr0_14	46
480 to 511	15	qmss_intr0_15	47

Table 5-6 shows the mapping of queues with queue pend signals tied to the chip-level CP-INTC0 interrupt controller. The mapping of queue number to CP-INTC input is fixed and cannot be changed.

Table 5-6 CPINTC Queue Mapping (TCI661x and C6670)

Queue	Interrupt Name	CPINTC0 Input Event
662	qm_int_pass_txq_pend_22	134
663	qm_int_pass_txq_pend_23	135
664	qm_int_pass_txq_pend_24	136
665	qm_int_pass_txq_pend_25	137
666	qm_int_pass_txq_pend_26	138
667	qm_int_pass_txq_pend_27	139
668	qm_int_pass_txq_pend_28	140
669	qm_int_pass_txq_pend_29	141
670	qm_int_pass_txq_pend_30	142
671	qm_int_pass_txq_pend_31	175

For example, to map queue 665 to trigger TCI6616 DSP event 57:

Map CP-INTC input 137 to CP-INTC (output) channel 1.
Enable system interrupt 137.
Enable DSP event 57.
(Repeat on each core you desire to handle the event.)