SLVUCR8A September 2023 – March 2024 TPS25751
- 1
- Read This First
- 1Introduction
- 2PD Controller Policy Modes
- 3TPS25751 Registers
-
44CC Task Detailed Descriptions
- 4.1 CPU Control Tasks
- 4.2
PD Message Tasks
- 4.2.1 'SWSk' - PD PR_Swap to Sink
- 4.2.2 'SWSr' - PD PR_Swap to Source
- 4.2.3 'SWDF' - PD DR_Swap to DFP
- 4.2.4 'SWUF' - PD DR_Swap to UFP
- 4.2.5 'GSkC' - PD Get Sink Capabilities
- 4.2.6 'GSrC' - PD Get Source Capabilities
- 4.2.7 'GPPI' - PD Get Port Partner Information
- 4.2.8 'SSrC' - PD Send Source Capabilities
- 4.2.9 'MBRd' - Message Buffer Read
- 4.3 Patch Bundle Update Tasks
- 4.4 System Tasks
- 5User Reference
- 6Revision History
5.2 Loading a Patch Bundle
The patch bundle can contain Application Customization data and a Patch binary that modifies the default application firmware in the PD controller. This section will describe how the host can load the patch bundle. The host uses the I2Ct bus for all transactions related to loading the patch bundle. As noted in the flow diagram below, the I2C target address varies depending upon which mode the PD controller is in. The Patch Burst Mode allows the host to push the Patch Bundle to multiple PD controllers simultaneously.
The following flow diagram illustrates the normal successful patch loading process. Other error handling steps can be necessary depending upon the nature of the errors encountered for a particular system. The EC can reset and restart the patch process by issuing a 'PBMe' 4CC Task.
The following table summarizes the target addresses in the different modes of operation.
| MODE Register Read-Back Value | I2Ct |
|---|---|
| Target Address 1 | |
| 'BOOT' | As configured by ADCINx pins. This is the "Fundamental" I2C target address. BOOT indicates that the PD controller is in the boot stage due to a bad firmware image or incorrect ADCINx settings. APP indicates that the firmware has successfully loaded and is in normal operation. PTCH indicates that the PD controller is waiting for a patch or is in the patch process using the PBMx commands. |
| 'PTCH'(1) | |
| 'APP '(2) |
Figure 5-1 Flow for Pushing a Patch Bundle Over the I2Ct Bus to Multiple PD Controllers at the Same TimeWhile the host is writing the Patch Bundle burst data, the I2C protocol in the following figure must be followed. The host can send the entire Patch Bundle in a single I2C transaction, or it can break it up into multiple transactions. The PD controller increments the pointer into its patch memory space with each byte received on the Patch Target address that was configured by DATA1.TargetAddress as part of the 'PBMs' 4CC Task. The EC can re-issue a 'PBMs' 4CC Task or it can issue a 'PBMe' 4CC Task in order to reset the pointer.
Figure 5-2 Protocol of Patch Bundle Burst Data Assuming it is Broken Into Two Transactions