SLVUCR8A September 2023 – March 2024 TPS25751
| Description | The 'PBMs' Task starts the patch loading sequence. This Task initializes the firmware in preparation for a patch bundle load sequence and indicates what the patch bundle will contain. | |||
|---|---|---|---|---|
| INPUT DATAX | Bit | Name | Description | |
| Byte 6: Burst Mode Timeout | ||||
| 7:6 | Reserved | |||
| 5:0 | Timeout value | Timeout value for this task. A non-zero value must be used, it is recommended to always use 0x32 in this field (5 seconds) (LSB of 100ms). | ||
| Byte 5: I2C target for downloading patch. | ||||
| 7 | Reserved | |||
| 6:0 | I2C Target Address | The following target addresses are not valid:
| ||
| Bytes 0-3: Low Region Binary bundle size in of bytes: [ Byte4, Byte3, Byte2, Byte1] | ||||
| 39:32 | Byte4 of bundle size | |||
| 31:24 | Byte3 of bundle size | |||
| 23:16 | Byte2 of bundle size | |||
| 15:8 | Byte1 of bundle size | |||
| OUTPUT DATAX | Bit | Name | Description | |
| 7:0 | PatchStartStatus | Status of the patch start. | ||
| 0x00 | Patch start success | |||
| 0x04 | Invalid bundle size | |||
| 0x05 | Invalid target address | |||
| 0x06 | Invalid Timeout value | |||
| Task Completion | The 'PBMs' Task completes after output has a valid PatchStartStatus. If MODE register (0x03) is equal to 'APP ', then this Task will be rejected. | |||
| Side Effects | When the 'PBMs' is successful, the second target address will be set to the input value. | |||
| Additional Information | The host can only issue a 'PBMs' Task to the I2Ct port of the PD controller. If the host issues 'PMBs' a second time, then the PD controller ignores the DATAX input, restarts the burst-mode timer, and resets the pointer to the beginning of the patch space in RAM. If the MODE register is 'APP ' indicating that the PD controller is in the APP mode, then it will reject the 'PBMs' Task. | |||