Three parallel TPS7A47 LDO's were configured for 12 VDC output voltage, supplying a combined 2.5 A load current, with a 60 mV maximum increase in load regulation (Figure 6-3). The TPS7A47 reference voltage is generated using a precision voltage source and is buffered with an internal unity gain amplifier see reference [3]. Thus, from Section 3.1 we tie the individual reference voltage pins together to reduce the current sharing imbalance among the three LDO's. The remaining error voltage is a function of the line regulation, load regulation and offset voltage variation. For the TPS7A47, the offset voltage across line and load is ± 4 mV worst case. We will set V_E = ± 4 mV in the analysis and from see reference [6], R_B = 61 m?. From Section 3, the highest load current for one LDO is when V_E is positive for one and negative for the rest. From Equation 10 we conclude I_OUT1 = 928 mA and I_OUT2 = I_OUT3 = 797 mA. We can determine the lowest load for an LDO by assuming one LDO has -V_E while the others have +V_E. From Equation 10 we conclude I_OUT1 = 753.5 mA and I_OUT2 = I_OUT3 = 885 mA.

The parallel LDO’s were implemented using EVM's and a post route simulation of the EVM identified 8.6 m? in the forward and return paths. Thus a 50 m? discrete ballast resistor was used for each LDO. Each output voltage was measured at V_IN = 15 V prior to connecting the EVM's together. Milliohm measurements were made of each ballast resistor (R4, R5 and R6) and the wire used to connect each EVM together (R7, R8 and R9), and these values were included in the spice simulation (Figure 6-4). Measurements versus simulation data in this configuration show strong correlation (Table 6-2).