3 ADC Driver Using OPAx328 High-Speed Op Amp

The OPAx328 are specifically designed to drive the input of high-speed, high-resolution analog-to-digital converters (ADCs). To filter out the noise as well as to minimize the disturbance to the input signal caused by ADC sample-and-hold current charge injection during converter sampling phase, a typical 1-nF to 10-nF output capacitor, C1, should be used. However, as with any op amp, a unity-gain (1-V/V) buffer configuration driving a large capacitive load exhibits a greatest tendency to become unstable compared to an amplifier operated in a higher noise gain. Thus, to assure stable operation of OPAx328, especially in the unity-gain configuration, a typical 10-Ω to 50-Ω resistor, R1, must be added in series with the output. This resistor significantly reduces the overshoot and ringing associated with large capacitive loads as well as helps to filter out noise before the signal is fed into the ADC input. Using 1-nF output capacitor, C1, requires R1 of at least 21 ? to assure OPAx328 recommended minimum phase margin of 45 degrees and results in the effective bandwidth to 13 MHz. A pole created at $f_P=\frac{1}{2\pi \times \left(45+21\right)\times {10}^{-9}}=2.4 MHz$ is canceled by a zero at $f_Z=\frac{1}{2\pi \times 21\times {10}^{-9}}=7.6 MHz$ and results in a quick recovery of the phase margin that assures stable operation of the buffer circuit, see Figure 3-1.

Running a small-signal transient simulation of the OPAx328 buffer driving 1-nF capacitor with 21-? series output resistor, R1, confirms stable operation of the circuit, see Figure 3-2.

However, if the output of the buffer amplifier includes a load resistor, R_L, this creates a resistive divider between Riso and R_L resistors that results in a gain error as shown in Figure 3-3. Thus, to eliminate the output voltage error, a dual feedback configuration might be used as shown in Figure 3-4.

The dual feedback configuration eliminates the output error with RF resistor driving the right side of the Riso resistor (thus controlling the DC output of the amplifier) while CF forms a buffer for AC signal by driving the left side of the Riso resistor, see Figure 3-5. This effectively duplicates fp/fz AC stability scheme employed in Figure 3-1 while eliminating DC output error caused by R_L loading shown in Figure 3-3. The appropriate values of R_F and C_F need to be carefully determined to optimize the transient settling time.

As was the case shown in Figure 3-2, performing a small-signal transient analysis confirms stable operation of the circuit with minimum ringing and optimal settling time, see Figure 3-6.