7.3.1 Detailed Pin Description

7.3.1.5 CBC (Cable Compensation)

The cable compensation pin is connected to a resistor to ground to program the amount of output voltage compensation needed to offset cable resistance. The cable compensation circuit generates a 0 to 3.13-V voltage level on the CBC pin corresponding to 0 A to I_OCC maximum output current. The resistance selected on the CBC pin programs a current mirror that is summed into the VS feedback divider therefore increasing the regulation voltage as I_OUT increases. There is an internal series resistance of 28 kΩ to the CBC pin which sets a maximum cable compensation for a 5-V output to approximately 400 mV when CBC is shorted to ground. The CBC resistance value can be determined using Equation 1.

Equation 1.

where

• V_CBC(max) is the maximum voltage at the cable compensation pin at the maximum converter output current (see Electrical Characteristics),
• V_OCV is the regulated output voltage,
• V_F is the diode forward voltage,
• V_VSR is the CV regulating level at the VS input (see Electrical Characteristics),
• V_OCBC is the target cable compensation voltage at the output terminals.

Note that the cable compensation does not change the overvoltage protection (OVP) threshold, V_OVP (see Electrical Characteristics), so the operating margin to OVP is less when cable compensation is used.

7.3.1.6 VS (Voltage Sense)

The VS pin connects to a resistor-divider from the auxiliary winding to ground and is used to sense input voltage, output voltage, event timing, and Wait-state wake-up signaling. The auxiliary voltage waveform is sampled at the end of the transformer secondary current demagnetization time to provide an accurate representation of the output voltage. The waveform on the VS pin determines the timing information to achieve valley-switching, and the timing to control the duty-cycle of the transformer secondary current when in Constant-Current Mode. Avoid placing a filter capacitor on this input which interferes with accurate sensing of this waveform.

During the MOSFET on-time, this pin also senses VS current generated through R_S1 by the reflected bulk-capacitor voltage to provide for AC-input Run and Stop thresholds, and to compensate the current-sense threshold across the AC-input range. For the AC-input Run/Stop function, the Run threshold on VS is 225 µA and the Stop threshold is 80 µA.

At the end of off-time demagnetization, the reflected output voltage is sampled at this pin to provide regulation and overvoltage protection. The values for the auxiliary voltage-divider upper-resistor, R_S1, and lower-resistor, R_S2, are determined by Equation 2 and Equation 3.

Equation 2.

where

• V_IN(run) is the target AC RMS voltage to enable turn-on of the controller (Run) (in case of DC input, leave out the √2 term in the equation),
• I_VSL(run) is the Run-threshold for the current pulled out of the VS pin during the switch on-time (see Electrical Characteristics),
• N_PA is the transformer primary-to-auxiliary turns-ratio.

Equation 3.

where

• V_OCV is the converter regulated output voltage,
• V_F is the output rectifier forward drop at near-zero current,
• N_AS is the transformer auxiliary-to-secondary turns-ratio,
• R_S1 is the VS divider high-side resistance,
• V_VSR is the CV regulating level at the VS input (see Electrical Characteristics).

When the UCC28730-Q1 is operating in the Wait state, the VS input is receptive to a wake-up signal superimposed upon the auxiliary winding waveform after the waveform meets either of two qualifying conditions. A high-level wake-up signal is considered to be detected if the amplitude at the VS input exceeds V_WU(high) (2 V) provided that any voltage at VS has been continuously below V_WU(high) for the wake-up qualification delay t_WDLY (8.5 us) after the demagnetization interval. A low-level wake-up signal is considered to be detected if the amplitude at the VS input exceeds V_WU(low) (57 mV) provided that any voltage at VS has been continuously below V_WU(low) for the wake-up qualification delay t_WDLY (8.5 us) after the demagnetization interval. The high-level threshold accommodates signals generated by a low-impedance secondary-side driver while the low-level threshold detects signals generated by a high-impedance driver.

7.3.1.7 CS (Current Sense)

The current-sense pin connects to a series resistor (R_LC) to the current-sense resistor (R_CS). The maximum current-sense threshold (V_CST(max)) is approximately 0.74 V for I_PP(max) and minimum current-sense threshold (V_CST(min)) is approximately 0.25 V for I_PP(min). R_LC provides the function of feed-forward line compensation to eliminate changes in I_PP with input voltage due to the propagation delay of the internal comparator and MOSFET turn-off time. An internal leading-edge blanking time of 225 ns eliminates sensitivity to the MOSFET turn-on current spike. It should not be necessary to place a bypass capacitor on the CS pin. The target output current in constant-current (CC) regulation determines the value of R_CS. The values of R_CS and R_LC are calculated by Equation 4 and Equation 5. The term V_CCR is the product of the demagnetization constant, 0.432, and V_CST(max). V_CCR is held to a tighter accuracy than either of its constituent terms. The term η_XFMR accounts for the energy stored in the transformer but not delivered to the secondary. This term includes transformer resistance and core loss, bias power, and primary-to-secondary leakage ratio.

Example: With a transformer core and winding loss of 5%, primary-to-secondary leakage inductance of 3.5%, and bias-power to output-power ratio of 0.5%, the η_XFMR value at full-power is: 1 - 0.05 - 0.035 - 0.005 = 0.91.

Equation 4.

where

• V_CCR is a constant-current regulation factor (see Electrical Characteristics),
• N_PS is the transformer primary-to-secondary turns-ratio, (a ratio of 13 to 15 is typical for a 5-V output),
• I_OCC is the target output current in constant-current regulation,
• η_XFMR is the transformer efficiency at full-power output.

Equation 5.

where

• K_LC is a current-scaling constant for line compensation (see Electrical Characteristics),
• R_S1 is the VS pin high-side resistor value,
• R_CS is the current-sense resistor value,
• N_PA is the transformer primary-to-auxiliary turns-ratio,
• t_D is the total current-sense delay consisting of MOSFET turn-off delay, plus approximately 50-ns internal delay,
• L_P is the transformer primary inductance.

7.3.2 Primary-Side Regulation (PSR)

Figure 13 illustrates a simplified isolated-flyback convertor with the main voltage regulation blocks of the device shown. The power train operation is the same as any DCM flyback circuit but accurate output voltage and current sensing is the key to primary-side control. The output voltage is sensed as a reflected voltage during the transformer demagnetization time using a divider network at the VS input. The primary winding current is sensed at the CS input using a current-sense resistor, R_CS.

Figure 13. Simplified Flyback Convertor (with the main voltage regulation blocks)

In primary-side control, the output voltage is indirectly sensed on the auxiliary winding at the end of the transfer of stored transformer energy to the secondary. As shown in Figure 14 it is clear there is a down slope representing a decreasing total rectifier V_F and resistance voltage drop as the secondary current decreases to zero. To achieve an accurate representation of the secondary output voltage on the auxiliary winding, the discriminator reliably blocks the leakage inductance reset and ringing, continuously samples the auxiliary voltage during the down slope after the ringing is diminished, and captures the error signal at the time the secondary winding reaches zero current. The internal reference on VS is 4.04 V. Temperature compensation on the VS reference voltage of -1 mV/°C offsets the change in the forward voltage of the output rectifier with temperature. The resistor divider is selected as outlined in the VS pin description.

Figure 14. Auxiliary Winding Voltage

The UCC28730-Q1 VS-signal sampler includes signal discrimination methods to ensure an accurate sample of the output voltage from the auxiliary winding. There are, however, some details of the auxiliary winding signal which require attention to ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any subsequent leakage inductance ring. Refer to Figure 15 below for a detailed illustration of waveform criteria to ensure a reliable sample on the VS pin.

Figure 15. Auxiliary Waveform Details

7.3.3 Primary-Side Constant Voltage Regulation

During voltage regulation, the controller operates in frequency modulation and amplitude modulation modes according to the control law as illustrated in Figure 16 below. The control law voltage V_CL reflects the internal operating level based on the voltage-error amplifier output signal. Neither of these signals is accessible to the user, however the approximate V_CL may be inferred from the frequency and amplitude of the current sense signal at the CS input. As the line and load conditions vary, V_CL adjusts the operating frequency and amplitude as required to maintain regulation of the output voltage. Because the UCC28730-Q1 incorporates internal loop compensation, no external stability compensation is required.

The internal operating frequency limits of the device are f_SW(max) and f_SW(min), typically 83.3 kHz and 32 Hz, respectively. The choice of transformer primary inductance and primary-peak current sets the maximum operating frequency of the converter, which must be equal to or lower than f_SW(max). Conversely, the choice of maximum target operating frequency and primary-peak current determines the transformer primary-inductance value. The actual minimum switching frequency for any particular converter depends on several factors, including minimum loading level, leakage inductance losses, switched-node capacitance losses, other switching and conduction losses, and bias-supply requirements. In any case, the minimum steady-state frequency of the converter must always exceed f_SW(min) or the output voltage may rise to the overvoltage protection level (OVP) and the controller responds as described in the Fault Protection Section.

The steady-state Control-Law voltage, V_CL, ranges between 1.3 to 4.85 V, depending on load, but may occasionally move below 0.75 V or above 4.85 V on load transients. Dropping below 0.75 V shifts the switching frequency to a lower range at light loads, while exceeding 4.85 V enters the constant-current mode of operation. There are 3 lower operating frequency ranges for progressively lighter loads, each overlapping the previous range to some extent, to provide stable regulation at very low frequencies. Peak-primary current is always maintained at I_PP(max)/3 in these lower frequency levels. Transitions between levels is automatically accomplished by the controller depending on the internal control-law voltage, V_CL.

Figure 16. Frequency and Amplitude Modulation Modes (during voltage regulation)

7.3.4 Primary-Side Constant Current Regulation

Timing information at the VS pin and current information at the CS pin allow accurate regulation of the secondary average current. The control law dictates that as power is increased in CV regulation and approaching CC regulation the primary-peak current will be at I_PP(max). Referring to Figure 17 below, the primary-peak current, turns ratio, secondary demagnetization time (t_DM), and switching period (t_SW) determine the secondary average output current. Ignoring leakage inductance effects, the average output current is given by Equation 6.

Figure 17. Transformer Currents Relationship

Equation 6.

When the average output current reaches the CC regulation reference in the current control block, the controller operates in frequency modulation mode to control the output current, I_OCC, at any output voltage down to or below the minimum operating voltage target, V_OCC (as seen in Figure 18), as long as the auxiliary winding can keep VDD voltage above the UVLO turn-off threshold. When V_O falls so low that VDD cannot be sustained above UVLO, the device shuts down.

Figure 18. Typical Output V-I Target Characteristic

7.3.5 Wake-Up Detection and Function

A major feature available at the VS pin is the wake-up function which operates in conjunction with a companion secondary-side wake-up device, such as the UCC24650. This feature allows light-load and no-load switching frequencies to approach 32 Hz to minimize losses, yet wake the UCC28730-Q1 from its wait state (sleep mode) in the event of a significant load step between power cycles. Despite the low frequencies, excessive output capacitance is not required to maintain reasonable transient response. While in the wait state, the UCC28730-Q1 continually monitors the VS input for a wake-up signal, and when detected, responds immediately with several high-frequency power cycles and resumes operation as required by the control law to recover from the load-step transient and restore output voltage regulation.

Because the wake-up feature interrupts the wait state between very low frequency switching cycles, it allows the use of a much lower output capacitance value than would be required to hold up the voltage without the wake-up function. It also allows the controller to drop to extremely low switching frequencies at no-load conditions to minimize switching losses. This facilitates the achievement of less than 5 mW of input power to meet zero-power stand-by requirements. Use of the UCC28730-Q1 controller alone cannot ensure zero-power operation since other system-level limitations are also imposed, however, the UCC28730-Q1 and UCC24650 combination goes a long way to reaching this goal.

Figure 19. Simplified Wake-Up Operation and Waveforms

The signals illustrated in Figure 19 refer to circuit nodes located on the 簡化電路原理圖 diagram on the first page of this datasheet. The wake-up signal, which is provided by a secondary-side driver, must meet certain criteria to be considered valid and recognized by the UCC28730-Q1 at the VS input. To distinguish the signal from the residual resonant ringing that follows a switching power cycle, the resonant ringing amplitude must diminish and remain below the wake-up signal detection threshold, V_WU, for a fixed qualification time, t_WUDLY.

The UCC28730-Q1 has two such thresholds; one at V_WU(low) and one at V_WU(high). The lower V_WU(low) threshold is used by converters which incorporate a relatively high-impedance driver for the wake-up signal, while the upper V_WU(high) threshold may be used in converters with a low-impedance wake-up driver. Both thresholds work exactly the same way. The advantage of the upper threshold is that the UCC28730-Q1 is qualified to accept a strong wake-up signal without waiting additional time for the resonant ringing to diminish below the lower threshold.

Figure 20 illustrates the qualification delay period and wake-up response to a low-level wake-up signal. Figure 21 illustrates the qualification delay period and wake-up response to a high-level wake-up signal.

Figure 20. Wake-Up Qualification Criteria and Wake-Up Response with Low Wake-Up Signal

Figure 21. Wake-Up Qualification Criteria and Wake-Up Response with High Wake-Up Signal

7.3.6 Valley-Switching and Valley-Skipping

The UCC28730-Q1 utilizes valley-switching to reduce switching losses in the MOSFET, to reduce induced-EMI, and to minimize the turn-on current spike at the current-sense resistor. The controller operates in valley-switching in all load conditions unless the V_DS ringing is diminished to the point where valleys are no longer detectable.

As shown in Figure 22, the UCC28730-Q1 operates in a valley-skipping mode (also known as valley-hopping) in most load conditions to maintain an accurate voltage or current regulation point and still switch on the lowest available V_DS voltage.

Figure 22. Valley-Skipping Mode

Valley-skipping modulates each switching cycle into discrete period durations. During FM operation, the switching cycles are periods when energy is delivered to the output in fixed packets, and the power delivered varies inversely with the switching period. During operating conditions when the switching period is relatively short, such as at high-load and low-line, the average power delivered per cycle varies significantly based on the number of valleys skipped between cycles. As a consequence, valley-skipping adds additional low-amplitude ripple voltage to the output with a frequency dependent upon the rate of change of the bulk voltage. For a load with an average power level between that of cycles with fewer valleys skipped and cycles with more valleys skipped, the voltage-control loop modulates the control law voltage and toggles between longer and shorter switching periods to match the required average output power.

7.3.7 Startup Operation

An internal high-voltage startup switch, connected to the bulk capacitor voltage (V_BULK) through the HV pin, charges the VDD capacitor. This startup switch functions similarly to a current source providing typically 250 µA to charge the VDD capacitor. When V_VDD reaches the 21-V UVLO turn-on threshold, the controller is enabled, the converter starts switching, and the startup switch turns off.

At initial turn-on, the output capacitor is often in a fully-discharged state. The first 4 switching-cycle current peaks are limited to I_PP(min) to monitor for any initial input or output faults with limited power delivery. After these 4 cycles, if the sampled voltage at VS is less than 1.32 V, the controller operates in a special startup mode. In this mode, the primary-current-peak amplitude of each switching cycle is limited to approximately 0.67 x I_PP(max) and D_MAGCC increases from 0.432 to 0.650. These modifications to I_PP(max) and D_MAGCC during startup allow high-frequency charge-up of the output capacitor to avoid audible noise while the demagnetization voltage is low. Once the sampled VS voltage exceeds 1.36 V, D_MAGCC is restored to 0.432 and the primary-current peak resumes as I_PP(max). While the output capacitor charges, the converter operates in CC mode to maintain a constant output current until the output voltage enters regulation. Thereafter, the controller responds to conditions as dictated by the control law. The time to reach output regulation consists of the time the VDD capacitor charges to V_VDD(on) plus the time the output capacitor charges.

7.3.8 Fault Protection

The UCC28730-Q1 provides comprehensive fault protection. The protection functions include:

1. Output Overvoltage
2. Input Undervoltage
3. Internal Overtemperature
4. Primary Overcurrent fault
5. CS-pin Fault
6. VS-pin Fault

A UVLO reset and restart sequence applies to all fault-protection events.

The output-overvoltage function is determined by the voltage feedback on the VS pin. If the voltage sample of VS exceeds 4.6 V for three consecutive switching cycles, the device stops switching and the internal current consumption becomes I_FAULT which discharges the VDD capacitor to the UVLO-turn-off threshold. After that, the device returns to the start state and a start-up sequence ensues.

Current into the VS pin during the MOSFET on time determines the line-input run and stop voltages. While the VS pin clamps close to GND during the MOSFET on time, the current through R_S1 is monitored to determine a sample of V_BULK. A wide separation of the run and stop thresholds allows clean start-up and shut-down of the power supply with line voltage. The run-current threshold is 225 µA and the Stop-current threshold is 80 µA. The input AC voltage to run at start-up always corresponds to the peak voltage of the rectified line, because there is no loading on C_BULK before start-up. The AC input voltage to stop varies with load since the minimum V_BULK depends on the loading and the value of C_BULK. At maximum load, the stop voltage is close to the run voltage, but at no-load condition the stop voltage can be approximately 1/3 of the run voltage.

The UCC28730-Q1 always operates with cycle-by-cycle primary-peak current control. The normal operating range of the CS pin is 0.74 to 0.249 V. An additional protection occurs if the CS pin reaches 1.5 V after the leading-edge blanking interval for three consecutive cycles, which results in a UVLO reset and restart sequence.

Normally at initial start-up, the peak level of the primary current of the first four power cycles is limited to the minimum V_CST(min). If the CS input is shorted or held low such that the V_CST(min) level is not reached within 4 µs on the first cycle, the CS input is presumed to be shorted to GND and the fault protection function results in a UVLO reset and restart sequence. Similarly, if the CS input is open, the internal voltage is pulled up to 1.5 V for three consecutive switching cycles and the fault protection function results in a UVLO reset and restart sequence.

The internal overtemperature-protection threshold is 165°C. If the junction temperature reaches this threshold, the device initiates a UVLO-reset cycle. If the temperature is still high at the end of the UVLO cycle, the protection cycle repeats.

Protection is included in the event of component failures on the VS pin. If complete loss of feedback information on the VS pin occurs, the controller stops switching and restarts.