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ZHCSAH7C November 2012 – June 2017 UCC28710 , UCC28711 , UCC28712 , UCC28713

PRODUCTION DATA.

封裝選項

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機械數(shù)據(jù) (封裝 | 引腳)

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings

See ⁽¹⁾.

			MIN	MAX	UNIT
V_HV	Start-up pin voltage, HV			700	V
V_VDD	Bias supply voltage, VDD			38	V
I_DRV	Continuous gate current sink			50	mA
I_DRV	Continuous gate current source			Self-limiting	mA
I_VS	Peak current, VS			−1.2	mA
V_DRV	Gate drive voltage at DRV		−0.5	Self-limiting	V
	Voltage	VS	−0.75	7	V
	Voltage	CS, CBC, NTC	−0.5	5	V
T_J	Operating junction temperature		−55	150	°C
	Lead temperature 0.6 mm from case for 10 s			260	°C
T_stg	Storage temperature		−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. These ratings apply over the operating ambient temperature ranges unless otherwise noted.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
VDD	Bias supply operating voltage	9	35	V
C_VDD	VDD bypass capacitor	0.047	1	µF
R_CBC	Cable-compensation resistance	10		kΩ
I_VS	VS pin current	−1		mA
T_J	Operating junction temperature	−40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		UCC2871x	UNIT
		D (SOIC)
		7 PINS
R_θJA	Junction-to-ambient thermal resistance	141.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	73.8	°C/W
R_θJB	Junction-to-board thermal resistance	89	°C/W
ψ_JT	Junction-to-top characterization parameter	23.5	°C/W
ψ_JB	Junction-to-board characterization parameter	88.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

over operating free-air temperature range, V_VDD = 25 V, HV = open, R_CBC(NTC) = open, T_A = –40 °C to 125 °C, T_A = T_J
(unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
HIGH-VOLTAGE START UP
I_HV	Start-up current out of VDD	V_HV = 100 V, V_VDD = 0 V, start state		100	250	500	µA
I_HVLKG	Leakage current at HV	V_HV = 400 V, run state			0.1	1	µA
BIAS SUPPLY INPUT
I_RUN	Supply current, run	I_DRV = 0, run state			2	2.65	mA
I_WAIT	Supply current, wait	I_DRV = 0, wait state			95	120	µA
I_START	Supply current, start	I_DRV = 0, V_VDD = 18 V, start state, I_HV = 0			18	30	µA
I_FAULT	Supply current, fault	I_DRV = 0, fault state			95	125	µA
UNDERVOLTAGE LOCKOUT
V_VDD(on)	VDD turnon threshold	V_VDD low to high		19	21	23	V
V_VDD(off)	VDD turnoff threshold	V_VDD high to low		7.7	8.1	8.5	V
VS INPUT
V_VSR	Regulating level	Measured at no-load condition, T_J = 25 °C⁽¹⁾		4.01	4.05	4.09	V
V_VSNC	Negative clamp level	I_VS = –300 µA, volts below ground		190	250	325	mV
I_VSB	Input bias current	V_VS = 4 V		–0.25	0	0.25	µA
CS INPUT
V_CST(max)	Maximum CS threshold voltage	V_VS = 3.7 V		738	780	810	mV
V_CST(min)	Minimum CS threshold voltage	V_VS = 4.35 V		175	195	215	mV
K_AM	AM control ratio	V_CST(max) / V_CST(min)		3.6	4	4.4	V/V
V_CCR	Constant current regulating level	CC regulation constant		318	330	343	mV
K_LC	Line compensation current ratio	I_VSLS = –300 µA, I_VSLS / current out of CS pin		24	25	28.6	A/A
T_CSLEB	Leading-edge blanking time	DRV output duration, V_CS = 1 V		180	235	280	ns
DRIVERS
I_DRS	DRV source current	V_DRV = 8 V, V_VDD = 9 V		20	25		mA
R_DRVLS	DRV low-side drive resistance	I_DRV = 10 mA			6	12	Ω
V_DRCL	DRV clamp voltage	V_VDD = 35 V			14	16	V
R_DRVSS	DRV pulldown in start state			150	190	230	kΩ
TIMING
f_SW(max)	Maximum switching frequency	V_VS = 3.7 V		92	100	106	kHz
f_SW(min)	Minimum switching frequency	V_VS = 4.35 V	UCC28710 UCC28711 UCC28712 UCC28713	600	680	755	Hz
t_ZTO	Zero-crossing timeout delay			1.8	2.1	2.55	µs
PROTECTION
V_OVP	Overvoltage threshold	At VS input, T_J = 25 °C⁽¹⁾		4.55	4.6	4.71	V
V_OCP	Overcurrent threshold	At CS input		1.4	1.5	1.6	V
I_VSL(run)	VS line-sense run current	Current out of VS pin increasing		190	225	275	µA
I_VSL(stop)	VS line-sense stop current	Current out of VS pin decreasing		70	80	100	µA
K_VSL	VS line sense ratio	I_VSL(run) / I_VSL(stop)		2.45	2.8	3.05	A/A
T_J(stop)	Thermal shut-down temperature	Internal junction temperature			165		°C
CABLE COMPENSATION
V_CBC(max)	Cable compensation maximum voltage	Voltage at CBC at full load	UCC28710	2.9	3.2	3.5	V
V_CVS(min)	Compensation at VS	V_CBC = open, change in VS regulating level at full load	UCC28710	–55	–15	25	mV
V_CVS(max)	Maximum compensation at VS	V_CBC = 0 V, change in VS regulating level at full load	UCC28710	275	320	375	mV
V_CVS	Compensation at VS	Change in VS regulating level at full load	UCC28711	–55	–15	25	mV
			UCC28712		103
			UCC28713		206
NTC INPUT
V_NTCTH	NTC shut-down threshold	Fault UVLO cycle when below this threshold	UCC28711 UCC28712 UCC28713	0.9	0.95	1	V
I_NTC	NTC pullup current	Current out of pin	UCC28711 UCC28712 UCC28713	90	105	125	µA

(1) The regulating level at VS decreases with temperature by 0.8 mV/?C. This compensation is included to reduce the power supply output voltage variance over temperature.