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ZHCSEQ1A February 2016 – February 2016 UCC28704

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DBV|6
- MPDS026Q

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

zhcseq1a_oa

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
V_VDD	Bias supply voltage		38	V
VS	Voltage range	–0.75	7	V
CS, NTC	Voltage range	–0.5	5	V
V_DRV	Gate-drive voltage at DRV	–0.5	Self-limiting	V
I_DRV	DRV continuous sink current		50	mA
I_DRV	DRV peak sourcing current, V_DRV = 10 V to 0 V		Self-limiting	mA
I_DRV	DRV peak sink current, V_DRV = 0 V to 10 V		Self-limiting	mA
I_VS	VS, peak, 1% duty-cycle, when detecting line voltage		1.2	mA
T_J	Operating junction temperature range	–55	150	°C
T_STG	Storage temperature	–65	150	°C
T_LEAD	Lead temperature 0.6 mm from case for 10 seconds		260	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM) ESD stress voltage⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
VDD	Bias supply operating voltage	8.5	35	V
C_DD	VDD bypass capacitor	0.047	no limit	µF
I_VS	VS pin sourcing current when detecting line voltage		1.0	mA
T_J	Operating junction temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC		UCC28704	UNIT
		DBV
		6 PINS
θ_JA	Junction-to-ambient thermal resistance ⁽¹⁾	150	°C/W
θ_JCtop	Junction-to-case (top) thermal resistance ⁽²⁾	55	°C/W
θ_JB	Junction-to-board thermal resistance ⁽³⁾	60	°C/W
ψ_JT	Junction-to-top characterization parameter ⁽⁴⁾	3	°C/W
ψ_JB	Junction-to-board characterization parameter ⁽⁵⁾	55	°C/W

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

6.5 Electrical Characteristics

Over operating free-air temperature range, V_VDD = 25 V, R_NTC = open, –40°C ≤ T_A ≤ 125°C, T_J = T_A (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
BIAS SUPPLY INPUT
I_RUN	Supply current, run	I_DRV = 0, run state	1.65	2.3	2.65	mA
I_WAIT	Supply current, wait	I_DRV = 0, V_VDD = 20 V, wait state	40	70	100	µA
I_START	Supply current, start	I_DRV = 0, V_VDD = 17 V, start state		1.5	2.5	µA
I_FAULT	Supply current, fault	I_DRV = 0, fault state	1.7	2.2	2.8	mA
UNDER-VOLTAGE LOCKOUT
V_VDD(on)	VDD turn-on threshold	V_VDD low to high	17.5	21	23	V
V_VDD(off)	VDD turn-off threshold	V_VDD high to low	7.3	7.7	8.15	V
VS INPUT
V_VSR	Regulating level ⁽¹⁾	Measured at no-load condition, T_J = 25°C	4.02	4.06	4.1	V
V_VSNC	Negative clamp level	I_VS = –300 µA	190	250	325	mV
I_VSB	Input bias current	V_VS = 4 V	–0.25	0	0.25	µA
CS INPUT
V_CST(max)	Max CS threshold voltage ⁽³⁾	V_VS = 3.70 V	720	750	784	mV
V_CST(min)	Min CS threshold voltage ⁽³⁾	V_VS = 4.35 V	170	187.5	210	mV
K_AM	AM control ratio	V_CST(max) / V_CST(min)	3.55	4	4.4	V/V
V_CCR	Constant-current regulating level		345	356	369	mV
K_LC	Line compensating current ratio, I_VSLS / (current out of CS pin)	I_VSLS = –300 µA	23	25	29	A/A
T_CSLEB	Leading-edge blanking time	DRV output duration, V_CS = 1 V	170	255	340	ns
DRV
I_DRS	DRV source current	V_DRV = 5 V, V_VDD = 9 V	25	32	38	mA
R_DRVLS	DRV low-side drive resistance	I_DRV = 10 mA		6.5	12	Ω
V_DRCL	DRV clamp voltage	V_VDD = 35 V	9.5	10.6	13	V
R_DRVSS	DRV pull-down in start state		165	205	250	kΩ
TIMING
f_SW(max)	Maximum switching frequency ⁽⁴⁾	V_VS = 3.7 V	78	85	94	kHz
f_SW(min)	Minimum switching frequency	V_VS = 4.6 V	0.88	1.03	1.18	kHz
t_ZTO	Zero-crossing timeout delay		1.7	2.39	3	µs
t_{CCUV_BLANK}	Blanking delay time before CCUV shutdown	V_VS step from 3.5 V to 2.4 V to DRV stop switching	90	120	150	ms
PROTECTION
K_OVP	Over-voltage threshold ratio to V_VSR	V_OVP/V_VSR	1.13	1.15	1.18	V/V
V_CCUV	CCUV V_O = 3.0 V	T_J = 25℃, auto restart after fault	2.41	2.48	2.55	V
V_OCP	Over-current threshold	At CS input	1.35	1.51	1.6	V
I_VSL(run)	VS line-sense run current	Current out of VS pin – increasing	190	220	265	µA
I_VSL(stop)	VS line-sense stop current	Current out of VS pin – decreasing	70	80	100	µA
K_VSL	VS line-sense ratio I_VSL(run) / I_VSL(stop)		2.55	2.8	2.95	A/A
T_J(stop)	Thermal shut-down temperature ⁽²⁾	Internal junction temperature		150		°C
CABLE COMPENSATION
V_CVS(max)	Maximum compensation at VS	Change in VS regulating level at full-load	180	220	260	mV
NTC INPUT
V_NTCTH	NTC shut-down threshold	VDD UVLO cycle when below this threshold	0.9	0.95	1	V
I_NTC	NTC pull-up current, out of pin	V_NTC = 1.1 V	90	100	120	µA

(1) The regulation level and OV threshold at VS decrease with increasing temperature by 1 mV/℃. This compensation over temperature is included to reduce the variances in power supply output regulation over-voltage detection with respect to the external output rectifier.

(2) Not tested in production.

(3) These threshold voltages represent average levels. This device automatically varies the current sense threshold to improve EMI performance.

(4) These frequency limits represent average levels. This device automatically varies the switching frequency to improve EMI performance.