ZHCSAO3E June 2013 – December 2014 UCC27527 , UCC27528
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 說(shuō)明（續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DSD|8
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DSD|8
訂購(gòu)信息
7 Specifications
7.1 Absolute Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply voltage range | VDD | –0.3 | 20.0 | V |
| OUTA, OUTB voltage | DC | –0.3 | VDD + 0.3 | |
| Repetitive pulse < 200 ns(4) | –2.0 | VDD + 0.3 | ||
| Output continuous source/sink current | IOUT_DC | 0.3 | A | |
| Output pulsed source/sink current (0.5 µs) | IOUT_pulsed | 5 | ||
| INA, INB, INA+, INA-, INB+, INB- voltage(3) | –6.5 | 20 | V | |
| ENA, ENB voltage(3) | –0.3 | 20 | ||
| Operating virtual junction temperature, TJ range | –40 | 150 | °C | |
| Lead temperature | Soldering, 10 s | 300 | ||
| Reflow | 260 | |||
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See Packaging Section of the datasheet for thermal limitations and considerations of packages.
(3) The maximum voltage on the Input and Enable pins is not restricted by the voltage on the VDD pin.
7.2 Handling Ratings
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Tstg | Storage temperature range | –65 | 150 | °C | |
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | –4000 | 4000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | –1000 | 1000 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|
| Supply voltage range, VDD | 4.5 | 12 | 18 | V |
| Operating junction temperature range | –40 | 140 | °C | |
| Input voltage, INA, INB, INA+, INA-, INB+, INB- | –5 | 18 | V | |
| Enable voltage, ENA and ENB | 0 | 18 |
7.4 Thermal Information
| THERMAL METRIC(1) | UCC27527, UCC27528 | UNIT | ||
|---|---|---|---|---|
| D | DSD | |||
| 8 PINS | 8 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 128 | 46.1 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 77.7 | 50.7 | |
| RθJB | Junction-to-board thermal resistance | 68.5 | 21.8 | |
| ψJT | Junction-to-top characterization parameter | 20.7 | 1.1 | |
| ψJB | Junction-to-board characterization parameter | 68.0 | 22.0 | |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | 9.0 | |
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
VDD = 12 V, TA = TJ = –40 °C to 140 °C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal (unless otherwise noted,)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| BIAS CURRENTS | |||||||
| IDD(off) | Startup current | VDD = 3.4 V, INA=VDD, INB=VDD |
UCC27528 | 55 | 125 | 225 | μA |
| UCC27527 | 55 | 180 | 270 | ||||
| VDD = 3.4 V, INA=GND, INB=GND |
UCC27528 | 25 | 125 | 225 | |||
| UCC27527 | 25 | 180 | 270 | ||||
| UNDERVOLTAGE LOCKOUT (UVLO) | |||||||
| VON | Supply start threshold | TJ = 25°C | 3.91 | 4.20 | 4.50 | V | |
| TJ = -40°C to 140°C | 3.75 | 4.20 | 4.65 | ||||
| VOFF | Minimum operating voltage after supply start | 3.60 | 3.90 | 4.40 | |||
| VDD_H | Supply voltage hysteresis | 0.20 | 0.30 | 0.50 | |||
| INPUTS (INA, INB, INA+, INA-, INB+, INB-), UCC2752X (D, DSD) | |||||||
| VIN_H | Input signal high threshold | Output high for non-inverting input pins Output low for inverting input pins |
55 | 70 | %VDD | ||
| VIN_L | Input signal low threshold | Output low for non-inverting input pins Output high for inverting input pins |
30 | 38 | |||
| VIN_HYS | Input hysteresis | 17 | |||||
| ENABLE (ENA, ENB) UCC2752X (D, DSD) | |||||||
| VEN_H | Enable signal high threshold | Output enabled | 1.7 | 1.9 | 2.1 | V | |
| VEN_L | Enable signal low threshold | Output disabled | 0.95 | 1.10 | 1.25 | ||
| VEN_HYS | Enable hysteresis | 0.70 | 0.80 | 1.10 | |||
| OUTPUTS (OUTA, OUTB) | |||||||
| ISNK/SRC | Sink/source peak current(1) | CLOAD = 0.22 µF, FSW = 1 kHz | ±5 | A | |||
| VDD-VOH | High output voltage | IOUT = -10 mA | 0.075 | V | |||
| VOL | Low output voltage | IOUT = 10 mA | 0.01 | ||||
| ROH | Output pull-up resistance(3) | IOUT = -10 mA | 2.5 | 5 | 7.5 | Ω | |
| ROL | Output pull-down resistance | IOUT = 10 mA | 0.15 | 0.5 | 1 | Ω | |
(1) Ensured by design.
(3) ROH represents on-resistance of only the P-Channel MOSFET device in pull-up structure of UCC2752X output stage.
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| tR | Rise time (2) | CLOAD = 1.8 nF, VDD = 10 V | 7 | ns | ||
| tF | Fall time(2) | CLOAD = 1.8 nF, VDD = 10 V | 6 | |||
| tM | Delay matching between 2 channels | INA = INB, OUTA and OUTB at 50% transition point, VDD = 10 V | 1 | 4 | ||
| tPW | Minimum input pulse width that changes the output state(2) | VDD = 10 V | 15 | |||
| tD1, tD2 | Input to output propagation delay (2) | CLOAD = 1.8 nF, 7-V input pulse, VDD = 10 V | 6 | 17 | 26 | |
| tD3, tD4 | EN to output propagation delay (2) | CLOAD = 1.8 nF, 7-V enable pulse, VDD = 10 V | 6 | 13 | 23 | |
Figure 1. Enable Function (For Non-Inverting Input Driver Operation)
Figure 3. Non-Inverting Input Driver Operation
Figure 2. Enable Function (For Inverting Input Driver Operation)
Figure 4. Inverting Input Driver Operation
7.7 Typical Characteristics
| VDD = 3.4 V | ||
| VDD = 12 V |
| VDD = 12 V |
| VDD = 12 V | IOUT = 10 mA |
| VDD = 10 V | CLOAD = 1.8 nF |
| VDD = 10 V |
| Both Channels Switching | CLOAD = 1.8 nF | |
| CLOAD = 1.8 nF |
| VDD = 4.5 V |
| VDD = 12 V | CLOAD = 500 pF | |
| fSW = 500 kHz | Both Channel Switching | |
| VDD = 12 V |
| VDD = 12 V | IOUT = 10 mA |
| VDD = 10 V | CLOAD = 1.8 nF |
| VDD = 10 V |
| CLOAD = 1.8 nF |
| CLOAD = 1.8 nF |