ZHCSFM4B september 2016 – december 2021 UCC21521
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Ratings
- 6.6 Insulation Specifications
- 6.7 Safety-Related Certifications
- 6.8 Safety-Limiting Values
- 6.9 Electrical Characteristics
- 6.10 Switching Characteristics
- 6.11 Insulation Characteristics Curves
- 6.12 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Designing INA/INB Input Filter
- 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
- 9.2.2.3 Gate Driver Output Resistor
- 9.2.2.4 Gate to Source Resistor Selection
- 9.2.2.5 Estimate Gate Driver Power Loss
- 9.2.2.6 Estimating Junction Temperature
- 9.2.2.7 Selecting VCCI, VDDA/B Capacitor
- 9.2.2.8 Dead Time Setting Guidelines
- 9.2.2.9 Application Circuits with Output Stage Negative Bias
- 9.2.3 Application Curves
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DW|16
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DW|16
訂購(gòu)信息
7.5 Powerup UVLO Delay to OUTPUT
Before the driver is ready to deliver a correct output state, there is a powerup delay from the UVLO rising edge to output and it is defined as tVCCI+ to OUT for VCCI UVLO (typically 40 μs) and tVDD+ to OUT for VDD UVLO (typically 50 μs). Consider the correct margin before launching the PWM signal after the driver's VCCI and VDD bias supplies are ready. Figure 7-5 and Figure 7-6 show the powerup UVLO delay timing diagram for VCCI and VDD.
If INA or INB are active before VCCI or VDD have crossed above their respective on thresholds, the output does not update until tVCCI+ to OUT or tVDD+ to OUT after VCCI or VDD crossing its UVLO rising threshold. However, when either VCCI or VDD receive a voltage less than their respective off thresholds, there is <1-μs delay, depending on the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay helps to ensure safe operation during VCCI or VDD brownouts.
Figure 7-5 VCCI Powerup UVLO Delay
Figure 7-6 VDDA/B Powerup UVLO Delay