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ZHCSKB9Q December 1999 – October 2019 UCC1895 , UCC2895 , UCC3895

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

J|20
- MGDI005
FK|20
- MCQC028

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6.5 Electrical Characteristics

V_DD = 12 V, R_T = 82 kΩ, C_T = 220 pF, R_DELAB = 10 kΩ, R_DELCD = 10 kΩ, C_REF = 0.1 μF, C_VDD = 0.1 μF and no load on the outputs, T_A = T_J. T_A = 0°C to 70°C for UCC3895x, T_A = –40°C to 85°C for UCC2895x and T_A = –55°C to 125°C for the UCC1895x (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
UVLO (UNDERVOLTAGE LOCKOUT)
UVLO_(on)	Start-up voltage threshold			10.2	11	11.8	V
UVLO_(off)	Minimum operating voltage after start-up			8.2	9	9.8	V
UVLO_(hys)	Hysteresis			1	2	3	V
SUPPLY
I_START	Start-up current	VDD = 8 V			150	250	µA
I_DD	Operating current				5	6	mA
V_{DD_CLAMP}	V_DD clamp voltage	IDD = 10 mA		16.5	17.5	18.5	V
VOLTAGE REFERENCE
V_REF	Output voltage	T_J = 25°C		4.94	5	5.06	V
V_REF	Output voltage	10 V < VDD < V_{DD_CLAMP}, 0 mA < IREF < 5 mA, temperature		4.85	5	5.15	V
I_SC	Short circuit current	REF = 0 V, T_J = 25°C		10	20		mA
ERROR AMPLIFIER
	Common-mode input voltage range			–0.1		3.6	V
V_IO	Offset voltage			–7		7	mV
I_BIAS	Input bias current (EAP, EAN)			–1		1	µA
EAOUT_{_VOH}	High-level output voltage	EAP – EAN = 500 mV, I_EAOUT = –0.5 mA		4	4.5	5	V
EAOUT_{_VOL}	Low-level output voltage	EAP – EAN = –500 mV, I_EAOUT = 0.5 mA		0	0.2	0.4	V
I_SOURCE	Error amplifier output source current	EAP – EAN = 500 mV, EAOUT = 2.5 V		1	1.5		mA
I_SINK	Error amplifier output sink current	EAP – EAN = –500 mV, EAOUT = 2.5 V		2.5	4.5		mA
A_VOL	Open-loop dc gain			75	85		dB
GBW	Unity gain bandwidth⁽¹⁾			5	7		mHz
	Slew rate⁽¹⁾	1 V < EAN < 0 V, EAP = 500 mV, 0.5 V < EAOUT < 3 V		1.5	2.2		V/µs
	No-load comparator turn-off threshold			0.45	0.5	0.55	V
	No-load comparator turn-on threshold			0.55	0.6	0.69	V
	No-load comparator hysteresis			0.035	0.1	0.165	V
OSCILLATOR
f_OSC	Frequency	T_J = 25°C		473	500	527	kHz
	Frequency total variation	Over line, temperature			2.5%	5%
V_{IH_SYNC}	SYNC input threshold, SYNC			2.05	2.1	2.4	V
V_{OH_SYNC}	High-level output voltage, SYNC	I_SYNC = –400 μA, V_CT = 2.6 V		4.1	4.5	5	V
V_{OL_SYNC}	Low-level output voltage, SYNC	I_SYNC = 100 μA, V_CT = 0 V		0	0.5	1	V
	Sync output pulse width	LOAD_SYNC = 3.9 kΩ and 30 pF in parallel			85	135	ns
V_RT	Timing resistor voltage			2.9	3	3.1	V
V_CT(peak)	Timing capacitor peak voltage			2.25	2.35	2.55	V
V_CT(valley)	Timing capacitor valley voltage			0	0.2	0.4	V
CURRENT SENSE
I_CS(bias)	Current sense bias current	0 V < CS < 2.5 V, 0 V ADS < 2.5 V		–4.5		20	µA
	Peak current threshold			1.9	2	2.1	V
	Overcurrent threshold			2.4	2.5	2.6	V
	Current sense to output delay	0 V ≤ CS ≤ 2.3 V, DELAB = DELCD = REF			75	110	ns
SOFT START/SHUTDOWN
I_SOURCE	Soft-start source current	SS/DISB = 3.0 V, CS = 1.9 V		–40	–35	–30	µA
I_SINK	Soft-start sink current	SS/DISB = 3.0 V, CS = 2.6 V		325	350	375	µA
	Soft-start/disable comparator threshold			0.44	0.5	0.56	V
ADAPTIVE DELAY SET (ADS)
	DELAB/DELCD output voltage	ADS = CS = 0 V		0.45	0.5	0.55	V
	DELAB/DELCD output voltage	ADS = 0 V, CS = 2 V		1.9	2	2.1	V
t_DELAY	Output delay⁽¹⁾⁽³⁾	ADS = CS = 0 V		450	560	620	ns
	ADS bias current	0 V < ADS < 2.5 V, 0 V < CS < 2.5 V		–20		20	µA
OUTPUT
V_OH	High-level output voltage (all outputs)	I_OUT = –10 mA, VDD to output			250	400	mV
V_OL	Low-level output voltage (all outputs)	I_OUT = 10 mA	UCC1895		150	300	mV
V_OL	Low-level output voltage (all outputs)	I_OUT = 10 mA	UCC2895, UCC3895		150	250	mV
t_R	Rise time⁽¹⁾	C_LOAD = 100 pF			20	35	ns
t_F	Fall time⁽¹⁾	C_LOAD = 100 pF			20	35	ns
PWM COMPARATOR
	EAOUT to RAMP input offset voltage	RAMP = 0 V, DELAB = DELCD = REF		0.72	0.85	1.05	V
	Minimum phase shift⁽²⁾ (OUTA to OUTC, OUTB to OUTD)	RAMP = 0 V, EAOUT = 650 mV		0.0%	0.85%	1.4%
t_DELAY	Delay⁽³⁾ (RAMP to OUTC, RAMP to OUTD)	0 V < RAMP < 2.5 V, EAOUT = 1.2 V, DELAB = DELCD = REF			70	120	ns
I_R(bias)	RAMP bias current	RAMP < 5 V, CT = 2.2 V		–5		5	µA
I_R(sink)	RAMP sink current	RAMP = 5 V, CT = 2.6 V	UCC1895	10	19		mA
I_R(sink)	RAMP sink current	RAMP = 5 V, CT = 2.6 V	UCC2895, UCC3895	12	19		mA

(1) Ensured by design. Not production tested.

(2) Minimum phase shift is defined as:
UCC1895 UCC2895 UCC3895 eq_note_slus157.gif

where

t_f(OUTA) = falling edge of OUTA signal
t_f(OUTB) = falling edge of OUTB signal
t_f(OUTC) = falling edge of OUTC signal
t_f(OUTD) = falling edge of OUTD signal
t_PERIOD = period of OUTA or OUTB signal

(3) Output delay is measured between OUTA and OUTB, or OUTC and OUTD. Output delay is defined as shown below where: t_f(OUTA) = falling edge of OUTA signal, t_r(OUTB) = rising edge of OUTB signal (see Figure 1 and Figure 2).

UCC1895 UCC2895 UCC3895 td1_b_d_slus157.gif

Figure 1. Same Applies to OUTB and OUTD

UCC1895 UCC2895 UCC3895 td2_c_d_slus157.gif

Figure 2. Same Applies to OUTC and OUTD