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ZHCS144I March 2011 – March 2016 TUSB9261

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

PVP|64
- MPQF055B

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)

		MIN	MAX	UNIT
V_DD	Steady-state supply voltage	–0.3	1.4	V
V_DD33/ V_DDA33	Steady-state supply voltage	–0.3	3.8	V
T_stg	Storage temperature	–55	150	°C

6.2 ESD Ratings

				VALUE	UNIT
V_ESD	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS001⁽¹⁾		±2000	V
V_ESD	Electrostatic discharge	Charged device model (CDM), per JESD22-C101⁽²⁾		±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
V_DD	Digital 1.1-V supply voltage		1.045	1.1	1.155	V
V_DD33	Digital 3.3-V supply voltage		3	3.3	3.6	V
V_DDA33	Analog 3.3-V supply voltage		3	3.3	3.6	V
V_BUS	Voltage at VBUS PAD		0		1.155	V
T_A	Operating free-air temperature range		0		70	°C
T_A	Operating free-air temperature range	Industrial version	–40		85	°C
T_J	Operating junction temperature range		–40		100	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TUSB9261	UNIT
		PVP (HTQFP)
		64 PINS
R_θJA	Junction-to-ambient thermal resistance	30.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	11.0	°C/W
R_θJB	Junction-to-board thermal resistance	6.1	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	6.1	°C/W
R_JθC(bot)	Junction-to-case (bottom) thermal resistance	0.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 DC Electrical Characteristics for 3.3-V Digital I/O

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DRIVER
T_R	Rise time	5 pF			1.5	ns
T_F	Fall time	5 pF			1.53	ns
I_OL	Low-level output current	V_DD33 = 3.3 V, T_J = 25°C		6		mA
I_OH	High-level output current	V_DD33 = 3.3 V, T_J = 25°C		–6		mA
V_OL	Low-level output voltage	I_OL = 2 mA			0.4	V
V_OH	High-level output voltage	I_OL = –2 mA	2.4			V
V_O	Output voltage		0		VDD33	V
RECEIVER
V_I	Input voltage		0		VDD33	V
V_IL	Low-level input voltage		0		0.8	V
V_IH	High-level input voltage		2			V
V_hys	Input hysteresis		200			mV
t_T	Input transition time (T_R and T_F)				10	ns
I_I	Input current	V_I = 0 V to V_DD33			5	µA
C_I	Input capacitance	V_DD33 = 3.3 V, T_J = 25°C		0.384		pF

6.6 SuperSpeed USB Power Consumption

POWER RAIL	TYPICAL ACTIVE CURRENT (mA)⁽¹⁾	TYPICAL SUSPEND CURRENT (mA)⁽²⁾
VDD11	291	153
VDD33⁽³⁾	65	28

(1) Transferring data by SS USB to a SSD SATA Gen II device. No SATA power management, U0 only.

(2) SATA Gen II SSD attached no active transfer. No SATA power management, U3 only.

(3) All 3.3-V power rails connected together.

6.7 High-Speed USB Power Consumption

POWER RAIL	TYPICAL ACTIVE CURRENT (mA)⁽¹⁾	TYPICAL SUSPEND CURRENT (mA)⁽²⁾
VDD11	172	153
VDD33⁽³⁾	56	28

(1) Transferring data via HS USB to a SSD SATA Gen II device. No SATA power management.

(2) SATA Gen II SSD attached no active transfer. No SATA power management.

(3) All 3.3-V power rails connected together.

6.8 Oscillator Specification

XI should be tied to the 1.8-V clock source and XO should be left floating. VSSOSC should be connected to the PCB ground plane. A 40-MHz clock can be used.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
C_XI	XI input capacitance	T_J = 25°C		0.414		pF
V_IL	Low-level input voltage				0.7	V
V_IH	High-level input voltage		1.05			V
T_{tosc_i}	Frequency tolerance	Operational temperature	–50		50	ppm
T_duty	Duty cycle		45%	50%	55%
T_R/T_F	Rise/fall time	20% to 80%			6	ns
R_J	Reference clock	JTF (1 sigma)⁽¹⁾⁽²⁾			0.8	ps
T_J	Reference clock	JTF (total p-p)⁽²⁾⁽³⁾			25	ps
T_p-p	Reference clock jitter	(Absolute p-p)⁽⁴⁾			50	ps

(1) Sigma value assuming Gaussian distribution

(2) After application of JTF

(3) Calculated as 14.1 × R_J + D_J

(4) Absolute phase jitter (p-p)

6.9 Crystal Specification

A parallel, 20-pF load capacitor should be used if a crystal source is used. VSSOSC should not be connected to the PCB ground plane. A 40-MHz crystal can be used.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Oscillation mode		Fundamental
ƒ_O	Oscillation frequency			40		MHz
ESR	Equivalent series resistance	40 MHz			50	Ω
T_{tosc_i}	Frequency tolerance	Operational temperature			±50	ppm
	Frequency stability	1 year aging			±50	ppm
C_L	Load capacitance		12	20	24	pF
C_SHUNT	Crystal and board stray capacitance				4.5	pF
	Drive level (max)				0.8	mW