ZHCS144I March 2011 – March 2016 TUSB9261
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- PVP|64
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
5 Pin Configuration and Functions
PVP Package
48-Pin HTQFP
Top View
Signal Descriptions – I/O Definitions
| I/O TYPE | DESCRIPTION |
|---|---|
| I | Input |
| O | Output |
| I/O | Input/output |
| PU | Internal pullup resistor |
| PD | Internal pulldown resistor |
| PWR | Power signal |
Clock and Reset Signals
SATA Interface Signals(1)
| PIN | I/O | DESCRIPTION | |||||||
|---|---|---|---|---|---|---|---|---|---|
| NAME | NO. | ||||||||
| SATA_TXP | 57 | O | Serial ATA transmitter differential pair (positive) | ||||||
| SATA_TXM | 56 | O | Serial ATA transmitter differential pair (negative) | ||||||
| SATA_RXP | 60 | I | Serial ATA receiver differential pair (positive) | ||||||
| SATA_RXM | 59 | I | Serial ATA receiver differential pair (negative) | ||||||
(1) Note that the default firmware and reference design for the TUSB9261 have the SATA TXP/TXM swapped for ease of routing in the reference design. If you plan to use the TI default firmware please review the reference design in the TUSB9261 DEMO User’s Guide (SLLU139) for proper SATA connection.
USB Interface Signals
| PIN | I/O | DESCRIPTION | |||||||
|---|---|---|---|---|---|---|---|---|---|
| NAME | NO. | ||||||||
| USB_SSTXP | 43 | O | SuperSpeed USB transmitter differential pair (positive) | ||||||
| USB_SSTXM | 42 | O | SuperSpeed USB transmitter differential pair (negative) | ||||||
| USB_SSRXP | 46 | I | SuperSpeed USB receiver differential pair (positive) | ||||||
| USB_SSRXM | 45 | I | SuperSpeed USB receiver differential pair (negative) | ||||||
| USB_DP | 36 | I/O | USB high-speed differential transceiver (positive) | ||||||
| USB_DM | 35 | I/O | USB high-speed differential transceiver (negative) | ||||||
| USB_VBUS | 50 | I | USB bus power | ||||||
| USB_R1 | 38 | O | Precision resistor reference. A 10-kΩ ±1% resistor should be connected between R1 and R1RTN. | ||||||
| USB_R1RTN | 39 | I | Precision resistor reference return | ||||||
Serial Peripheral Interface (SPI) Signals
| PIN | I/O | DESCRIPTION | |||||||
|---|---|---|---|---|---|---|---|---|---|
| NAME | NO. | ||||||||
| SPI_SCLK | 17 | O PU |
SPI clock | ||||||
| SPI_DATA_OUT | 18 | O PU |
SPI master data out | ||||||
| SPI_DATA_IN | 20 | I PU |
SPI master data in | ||||||
| SPI_CS0 | 21 | O PU |
Primary SPI chip select for flash RAM | ||||||
| SPI_CS2/ | 23 | I/O PU |
SPI chip select for additional peripherals. When not used for SPI chip select, this pin may be used as a general-purpose I/O. | ||||||
| GPIO11 | |||||||||
| SPI_CS1/ | 22 | I/O PU |
SPI chip select for additional peripherals. When not used for SPI chip select, this pin may be used as a general-purpose I/O. | ||||||
| GPIO10 | |||||||||
JTAG, GPIO, and PWM Signals
| PIN | I/O | DESCRIPTION | |||||||
|---|---|---|---|---|---|---|---|---|---|
| NAME | NO. | ||||||||
| JTAG_TCK | 25 | I PD |
JTAG test clock | ||||||
| JTAG_TDI | 26 | I PU |
JTAG test data in | ||||||
| JTAG_TDO | 27 | O PD |
JTAG test data out | ||||||
| JTAG_TMS | 28 | I PU |
JTAG test mode select | ||||||
| JTAG_TRSTz | 29 | I PD |
JTAG test reset | ||||||
| GPIO9/UART_TX | 6 | I/O PU |
GPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a UART channel. This pin defaults to a general-purpose output. | ||||||
| GPIO8/UART_RX | 5 | I/O PU |
GPIO/UART receiver. This terminal can be configured as a GPIO or as the receiver for a UART channel. This pin defaults to a general-purpose output. | ||||||
| GPIO7 | 16 | I/O PD |
Configurable as general-purpose input/outputs | ||||||
| GPIO6 | 15 | I/O PD |
|||||||
| GPIO5 | 14 | I/O PD |
|||||||
| GPIO4 | 13 | I/O PD |
|||||||
| GPIO3 | 11 | I/O PD |
|||||||
| GPIO2 | 10 | I/O PD |
|||||||
| GPIO1 | 9 | I/O PD |
|||||||
| GPIO0 | 8 | I/O PD |
|||||||
| PWM0 | 2 | O PD(1) |
Pulse-width modulation (PWM). Can be used to drive status LEDs. | ||||||
| PWM1 | 3 | O PD(1) |
|||||||
(1) PWM pulldown resistors are disabled by default. A firmware modification is required to turn them on. All other internal pull up/down resistors are enabled by default.
Power and Ground Signals
| PIN | I/O | DESCRIPTION | |||||||
|---|---|---|---|---|---|---|---|---|---|
| NAME | NO. | ||||||||
| VDD | 1 | PWR | 1.1-V power rail | ||||||
| 12 | |||||||||
| 19 | |||||||||
| 32 | |||||||||
| 33 | |||||||||
| 41 | |||||||||
| 47 | |||||||||
| 49 | |||||||||
| 55 | |||||||||
| 61 | |||||||||
| 63 | |||||||||
| VDD33 | 7 | PWR | 3.3-V power rail | ||||||
| 24 | |||||||||
| 51 | |||||||||
| VDDA33 | 34 | PWR | 3.3-V analog power rail | ||||||
| 40 | |||||||||
| 48 | |||||||||
| 62 | |||||||||
| VSSOSC | 53 | PWR | Oscillator ground. If using a crystal, this should not be connected to a PCB ground plane. If using an oscillator, this should be connected to PCB ground. See Clock Source Requirements for more details. | ||||||
| VSS | 44 | PWR | Ground | ||||||
| 58 | |||||||||
| VSS | 65 | PWR | Ground – Thermal pad | ||||||
| NC | 37 | — | No connect, leave floating | ||||||
| 64 | |||||||||