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ZHCSE04D August 2015 – May 2017 TUSB320HI , TUSB320LI

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RWB|12
- MPQF391C

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	V_DD	–0.3	6.0	V
Control pins	CC1, CC2, PORT, ADDR, ID, EN_N, INT_N/OUT3	–0.3	V_DD + 0.3	V
	CC1, CC2	–0.3	6
	SDA/OUT1, SCL/OUT2	–0.3	V_DD + 0.3
	VBUS_DET , EN	–0.3	4
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±5000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_DD	Supply voltage range	2.7		5	V
V_BUS	System V_BUS voltage	4	5	28	V
T_A	TUSB320HI and TUSB320LI Operating free air temperature range	–40	25	85	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TUSB320	UNIT
		RWB (X2QFN)
		12 PINS
R_θJA	Junction-to-ambient thermal resistance	169.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	68.1	°C/W
R_θJB	Junction-to-board thermal resistance	83.4	°C/W
ψ_JT	Junction-to-top characterization parameter	2.2	°C/W
ψ_JB	Junction-to-board characterization parameter	83.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and C Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Power Consumption
I_{UNATTACHED_UFP}	Current consumption in unattached mode when port is unconnected and waiting for connection. [V_DD = 4.5 V, EN_N (TUSB320L) = L, EN (TUSB320H) = H, ADDR = NC, PORT = L]			100		µA
I_{ACTIVE_UFP}	Current consumption in active mode. (V_DD = 4.5 V, EN_N (TUSB320L) = L, EN (TUSB320H) = H, ADDR = NC, PORT = L)			100		µA
I_SHUTDOWN	Leakage current when V_DD is supplied, but the TUSB320 device is not enabled. (V_DD = 4.5 V, EN_N (TUSB320L) = H, EN (TUSB320H) = L)			0.040		µA
CC1 and CC2 Pins
R_{CC_DB}	Pulldown resistor when in dead-battery mode.		4.1	5.1	6.1	kΩ
R_{CC_D}	Pulldown resistor when in UFP or DRP mode.		4.6	5.1	5.6	kΩ
V_{TH_UFP_CC_USB}	Voltage threshold for detecting a DFP attach when configured as a UFP and DFP is advertising default current source capability.		0.15	0.2	0.25	V
V_{TH_UFP_CC_MED}	Voltage threshold for detecting a DFP attach when configured as a UFP and DFP is advertising medium (1.5 A) current source capability.		0.61	0.66	0.7	V
V_{TH_UFP_CC_HIGH}	Voltage threshold for detecting a DFP attach when configured as a UFP and DFP is advertising high (3 A) current source capability.		1.169	1.23	1.29	V
V_{TH_DFP_CC_USB}	Voltage threshold for detecting a UFP attach when configured as a DFP and advertising default current source capability.		1.51	1.6	1.64	V
V_{TH_DFP_CC_MED}	Voltage threshold for detecting a UFP attach when configured as a DFP and advertising medium current (1.5 A) source capability.		1.51	1.6	1.64	V
V_{TH_DFP_CC_HIGH}	Voltage threshold for detecting a UFP attach when configured as a DFP and advertising high current (3.0 A) source capability.		2.46	2.6	2.74	V
I_{CC_DEFAULT_P}	Default mode pullup current source when operating in DFP or DRP mode.		64	80	96	µA
I_{CC_MED_P}	Medium (1.5 A) mode pullup current source when operating in DFP or DRP mode.		166	180	194	µA
I_{CC_HIGH_P}	High (3 A) mode pullup current source when operating in DFP or DRP mode.⁽¹⁾		304	330	356	µA
Control Pins: PORT, ADDR, INT/OUT3, EN_N, EN, ID
V_IL	Low-level control signal input voltage (PORT, ADDR, EN_N, EN)				0.4	V
V_IM	Mid-level control signal input voltage (PORT, ADDR)		0.28 × V_DD		0.56 × V_DD	V
V_IH	High-level control signal input voltage (PORT, ADDR, EN_N)		V_DD - 0.3		V_DD	V
V_{IH_EN}	High-Level control signal input voltage for EN for TUSB320H		1.05		3.65	V
I_IH	High-level input current		–20		20	µA
I_IL	Low-level input current		–10		10	µA
R_{EN_N}	Internal pullup resistance for EN_N for TUSB320L			1.1		MΩ
R_EN	Internal pulldown resistance for EN for TUSB320H			500		kΩ
R_pu⁽²⁾	Internal pullup resistance (PORT, ADDR)			588		kΩ
R_pd⁽²⁾	Internal pulldown resistance (PORT, ADDR)			1.1		MΩ
V_OL	Low-level signal output voltage (open-drain) (INT_N/OUT3, ID)	I_OL = –1.6 mA			0.4	V
R_{p_ODext}	External pullup resistor on open drain IOs (INT_N/OUT3, ID)			200		kΩ
R_{p_TLext}	Tri-level input external pullup resistor (PORT, ADDR)			4.7		kΩ
I²C - SDA/OUT1, SCL/OUT2 can operate from 1.8 or 3.3 V (±10%)⁽³⁾
V_{DD_I2C}	Supply range for I²C (SDA/OUT1, SCL/OUT2)		1.65	1.8	3.6	V
V_IH	High-level signal voltage		1.05		3.6	V
V_IL	Low-level signal voltage				0.4	V
V_OL	Low-level signal output voltage (open drain)	I_OL = –1.6 mA			0.4	V
VBUS_DET IO Pins (Connected to System V_BUS signal)
V_{BUS_THR}	V_BUS threshold range	See Figure 1	2.95	3.30	3.80	V
R_VBUS	External resistor between V_BUS and VBUS_DET pin		855	887	920	KΩ
R_{VBUS_PD}	Internal pulldown resistance for VBUS_DET			95		KΩ

(1) V_DD must be 3.5 V or greater to advertise 3 A current.

(2) Internal pullup and pulldown for PORT and ADDR are removed after the device has sampled EN = high or EN_N = low.

(3) When using 3.3 V for I²C, customer must ensure V_DD is above 3 V at all times.

6.6 Timing Requirements

		MIN	MAX	UNIT
I²C (SDA, SCL)
t_SU:DAT	Data setup time	100		ns
t_HD;DAT	Data hold time	10		ns
t_SU:STA	Set-up time, SCL to start condition	0.6		µs
t_HD:STA	Hold time (repeated), start condition to SCL	0.6		µs
t_SU:STO	Set up time for stop condition	0.6		µs
t_BUF	Bus free time between a stop and start condition	1.3		µs
t_VD;DAT	Data valid time		0.9	µs
t_VD;ACK	Data valid acknowledge time		0.9	µs
f_SCL	SCL clock frequency; I²C mode for local I²C control		400	kHz
t_r	Rise time of both SDA and SCL signals		300	ns
t_f	Fall time of both SDA and SCL signals		300	ns
C_{BUS_100KHZ}	Total capacitive load for each bus line when operating at ≤ 100 kHz		400	pF
C_{BUS_400KHz}	Total capacitive load for each bus line when operating at 400 kHz		100	pF

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_{CCCB_DEFAULT}	Power on default of CC1 and CC2 voltage debounce time	DEBOUCE register = 2'b00		168		ms
t_{VBUS_DB}	Debounce of VBUS_DET pin after valid V_{BUS_THR}			2		ms
t_{DRP_DUTY_CYCLE}	Power-on default of percentage of time DRP advertises DFP during a T_DRP	DRP_DUTY_CYCLE register = 2'b00		30%
t_DRP	The period during which the TUSB320 in DFP mode completes a DFP to UFP and back advertisement.		50	75	100	ms
t_{I2C_EN}	Time from TUSB320L's EN_N low or TUSB320H's EN high and V_DD active to I²C access available				100	ms
t_{SOFT_RESET}	Soft reset duration		26	49	95	ms

TUSB320HI TUSB320LI tvbus_db_sllsen9_320.gif

Figure 1. VBUS Detect and Debounce