ZHCSFS7B December 2016 – July 2017 TPSM84A22
PRODUCTION DATA.
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 21 and Figure 23 show typical, top-side PCB layouts. Some considerations for an optimized layout are:
The layout shown in Figure 21 shows the minimum solution size with only a single voltage setting resistor (R1) as the only additional required component. Figure 22 shows a typical internal PCB layer with a trace connecting the VS+ pin to VOUT near the load.
Figure 21. Minimum Component Layout
Figure 22. VS+ Trace on Internal Layer
Figure 23 shows a layout with the placement of additional ceramic input capacitors (C1, C3) and ceramic output capacitors (C2, C4) for designs that require additional ripple reduction or improved transient response. Figure 24 shows a typical internal PCB layer with a trace connecting the VS+ pin to VOUT near the load.
Figure 23. Layout with Optional CIN and COUT
Figure 24. VS+ Trace on Internal Layer
The TPSM84A22 is compliant with EN55022 Class B radiated emissions. Figure 25 to Figure 28 show typical examples of radiated emissions plots for the TPSM84A22. Graphs included show plots of the antenna in the horizontal and vertical positions.
Figure 25. Radiated Emissions 12-V Input, 1.2-V Output,
Figure 26. Radiated Emissions 12-V Input, 1.2-V Output,