ZHCSLW0A September 2020 – December 2020 TPSM41625
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Setting the Output Voltage
- 7.3.2 Output Voltage Current Rating
- 7.3.3 RS+/RS- Remote Sense Function
- 7.3.4 Ramp Select (RAMP and RAMP_SEL)
- 7.3.5 Switching Frequency (RT)
- 7.3.6 Synchronization (SYNC)
- 7.3.7 Stand-alone/Stackable Operation
- 7.3.8 Improved Transient Performance versus Fixed Frequency (Stand-alone Operation Only)
- 7.3.9 Output On/Off Enable (EN)
- 7.3.10 Power Good (PGOOD)
- 7.3.11 Soft-Start Operation
- 7.3.12 Input Capacitor Selection
- 7.3.13 Output Capacitor Selection
- 7.3.14 Current Limit (ILIM)
- 7.3.15 Safe Start-up into Pre-Biased Outputs
- 7.3.16 Overcurrent Protection
- 7.3.17 Output Overvoltage and Undervoltage Protection
- 7.3.18 Overtemperature Protection
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- MOV|69
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.3.7.1.4 Configuration 2: Dual Phase, Primary and Secondary Sync to External System Clock
- Direct connection between external clock and SYNC pin of primary and secondary.
- Direct VSHARE and ISHARE connections between primary and secondary.
- SYNC pin of primary is configured as sync in by its MODE pin.
- Primary and secondary receive external system clock from SYNC pin. Their RT pin determine the sync point for clock phase shift.
Figure 7-6 2-Phase
Stackable, 180° Phase Shift: Primary and Secondary Sync to
External System Clock