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ZHCSCS9 SEPTEMBER 2014 TPS92661-Q1

PRODUCTION DATA.

封裝選項(xiàng)

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

Over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Input voltage	VIN, VCC to GND	–0.3	7	V
	CPP to GND	–0.3	67
	CPP to LED12	–0.3	7
	LEDx to GND	–0.3	60
	LEDx to LED(x-1)	–0.3	7
	SYNC, EN, CLK, TX, RX, ADR0-2 to GND	–0.3	7

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales/Office/Distributors for availability and specifications.

6.2 Handling Ratings

				MIN	MAX	UNIT
T_stg	Storage temperature range			–40	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002 ⁽¹⁾		–2000	2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per AEC Q100-011	ALL Pins	–750	750	V

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_IN	Supply input voltage range		4.5	5.5	V
V_I	Input voltage range per channel	LEDx to LED(x-1)		5.0	V
I_O	Output current range		Thermally Limited		A
f_CLK	CLK frequency⁽¹⁾		0.1	16	MHz
D_CLK	CLK duty cycle		40%	60%
t_EW	EN input pulse width low		50		ns
t_ESS	EN setup to serial start		24/f_CLK		s
t_SW	SYNC input pulse width		1/f_CLK		s
V_IH	High-level input voltage		1.9	V_VCC + 0.3 V	V
V_IL	Low-level input voltage		GND – 0.3 V	0.8	V
T_A	Ambient temperature		–40	125	°C
T_J	Junction temperature		–40	150	°C

(1) Minimum f_clk is applicable only when CKWEN bit is set. f_clk down to 0Hz is possible when bit is not set.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS92661	UNITS
		TQFP
		48 pins
R_θJA	Junction-to-ambient thermal resistance	25.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	10.5
R_θJB	Junction-to-board thermal resistance	6.1
ψ_JT	Junction-to-top characterization parameter	0.2
ψ_JB	Junction-to-board characterization parameter	6.0
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Limits apply over operating junction temperature range –40°C ≤ T_J ≤ +150°C. Typical values represent the most likely parametric norm at T_J = 25°C. Unless otherwise noted, V_IN = 5 V. For digital outputs, C_LOAD = 20 pF.

PARAMETER		CONDITIONS	MIN	TYP	MAX	UNITS
GENERAL
I_VIN-OP	Input operating bias current	No switching		1		mA
V_IN-UVT	VIN internal POR threshold	VIN rising			4.5	V
V_CC-REG	Regulated VCC voltage	0 mA ≤ I_VCC ≤ 5 mA	3.1	3.3	3.5	V
I_VCC-LIM	VCC current limit			10		mA
V_CPP	Charge pump operating voltage	V_VIN = 5 V, V_SW = 0 V – 60 V		6.2		V
f_CPP	Charge pump oscillator frequency		1.3	2.3	3.3	MHz
LED MATRIX SWITCHES
R_DS(on)	LED switch on-resistance ⁽²⁾			225		mΩ
R_ALL(on)	All switches on-resistance	Measured LED12 - LED0		1800	3400	mΩ
I_DS(off)	OFF state switch leakage current				50	µA
V_TH-S	LED short threshold voltage	V_SW = 0 V – 60 V	0.52		1.4	V
V_TH-O	LED OPEN threshold voltage	V_SW = 0 V – 60 V	5	6	6.9	V
t_TO-O	LED OPEN detection and correction delay			50	150	ns
t_REP	LED fault reporting delay				5	µs
t_RISE(LEDx)	LEDx drain voltage rise time⁽¹⁾	I_LED = 800 mA		2		µs
t_FALL(LEDx)	LEDx drain voltage fall time⁽¹⁾	I_LED = 800 mA		2		µs
DIGITAL SPECIFICATIONS
V_IH-TH	High-level input voltage threshold				1.9	V
V_IL-TH	Low-level input voltage threshold		0.8			V
V_OH	High-level output voltage	I_SOURCE = 2 mA, V_VCC = 4.0 V	4.27			V
V_OL	Low-level output voltage	I_SINK = 2 mA, V_VCC = 4.5 V			0.23	V
I_OS	Output short circuit current (source or sink)	V_VCC = 4.5 V		42		mA
R_SP	Internal SYNC pull-down			100		kΩ
t_WD-TO	CLK watchdog timeout			32/f_CPP		µs
t_TO	CLK rise to TX output valid⁽¹⁾			80		ns
t_TZ	CLK rise to TX output tri-state⁽¹⁾			80		ns

(1) Specified by design. Not production tested.

(2) Single channel on-resitance (R_DS(on)) measurement includes internal bond wires. All switches on-resistance (R_ALL(on)) should be used for all power calculations. See Internal Switch Resistance for details.