ZHCSIY0 October 2018 TPS92515AHV-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 General Operation
- 8.3.2 Current Sense Comparator
- 8.3.3 OFF Timer
- 8.3.4 OFF-Timer, Shunt FET Dimming or Shunted Output Condition
- 8.3.5 Internal N-channel MOSFET
- 8.3.6 VCC Internal Regulator and Undervoltage Lockout (UVLO)
- 8.3.7 Analog Adjust Input
- 8.3.8 Thermal Protection
- 8.3.9 Junction Temperature Relative Estimation
- 8.3.10 BOOT and BOOT UVLO
- 8.3.11 PWM (UVLO and Enable)
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 General Design Procedure
- 9.2.2 Design Requirements
- 9.2.3
Detailed Design Procedure
- 9.2.3.1 Calculating Duty Cycle
- 9.2.3.2 Calculate OFF-Time Estimate
- 9.2.3.3 Calculate OFF-Time Resistor ROFF
- 9.2.3.4 Calculate the Inductance Value
- 9.2.3.5 Calculate the Sense Resistance
- 9.2.3.6 Calculate Input Capacitance
- 9.2.3.7 Verify Peak Current for Inductor Selection
- 9.2.3.8 Calculate Output Capacitance
- 9.2.3.9 Calculate UVLO Resistance Values
- 9.2.4 Application Curves
- 9.3 Dos and Don'ts
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DGQ|10
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DGQ|10
訂購信息
12.5 靜電放電警告
這些裝置包含有限的內(nèi)置 ESD 保護。 存儲或裝卸時，應(yīng)將導(dǎo)線一起截短或?qū)⒀b置放置于導(dǎo)電泡棉中，以防止 MOS 門極遭受靜電損傷。