SLVSK53 October 2025 TPS7E82
ADVANCE INFORMATION
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Detailed Description
-
7 Application and Implementation
- 7.1
Application Information
- 7.1.1 Adjustable Device Feedback Resistor Selection
- 7.1.2 Recommended Capacitor Types
- 7.1.3 Input and Output Capacitor Selection
- 7.1.4 Reverse Current
- 7.1.5 Feed-Forward Capacitor
- 7.1.6 Dropout Voltage
- 7.1.7 Estimating Junction Temperature
- 7.1.8 Power Dissipation (PD)
- 7.1.9 Power Dissipation Versus Ambient Temperature
- 7.2 Typical Application
- 7.1
Application Information
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
7.1.9 Power Dissipation Versus Ambient Temperature
Figure 7-2, Figure 7-3 and Figure 7-4 are based off of a JESD51-7 4-layer, high-K board. The allowable power dissipation is estimated using the following equation. As discussed in the An empirical analysis of the impact of board layout on LDO thermal performance application note, thermal dissipation can be improved in the JEDEC high-K layout by adding top layer copper and increasing the number of thermal vias. If a good thermal layout is used, the allowable thermal dissipation can be improved by up to 50%.
Equation 14.
Figure 7-2 TPS7E82 (DBV) Allowable
Power Dissipation
Figure 7-3 TPS7E82 (DRV) Allowable
Power Dissipation
Figure 7-4 TPS7E82 (DGN) Allowable Power Dissipation