SBVS463 October 2025 TPS7E81-Q1
ADVANCE INFORMATION
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Detailed Description
-
7 Application and Implementation
- 7.1
Application Information
- 7.1.1 Adjustable Device Feedback Resistor Selection
- 7.1.2 Recommended Capacitor Types
- 7.1.3 Input and Output Capacitor Selection
- 7.1.4 Reverse Current
- 7.1.5 Feed-Forward Capacitor
- 7.1.6 Dropout Voltage
- 7.1.7 Estimating Junction Temperature
- 7.1.8 Power Dissipation (PD)
- 7.1.9 Power Dissipation Versus Ambient Temperature
- 7.2 Typical Application
- 7.3 Power Supply Recommendations
- 7.4 Layout
- 7.1
Application Information
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
6.3.6 Power Limit
The device has an internal over-power limit circuit that limits the power dissipated across the LDO with-in the internal SOA (safe operating area) limits. The SOA limits for the LDO factors in safe operation for both silicon components, and bondwires used in packaging. These limits verify reliable operation of the device and prevent the device failure from overheating, breakdown, or other damaging effects.
The power dissipated (PDissip) across the LDO is defined by voltage drop across LDO (VIN - VOUT) and load current (IL) flowing through.
The power limiting circuit, monitors both the voltage drop (headroom, VIN - VOUT) across LDO and output load current (IOUT) flowing through. If PDissip crosses the defined SOA limits, the power limiting circuit, limits the load current (IOUT) flowing through. The output voltage is not regulated when the device is in Power limit operation. The maximum supported current (IPLIMIT) at full headroom (VIN - VOUT = 40V) and Max supported headroom (VPHEADROOM) at full load current are captured in Section 5.5.
Figure 6-6 shows a diagram of the power limiting.
Figure 6-6 Power Limiting