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ZHCSF73A March 2016 – July 2016 TPS7A89

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RTJ|20
- MPQF156F

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

RTJ|20
- QFND016S

訂購(gòu)信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range and all voltages with respect to GND (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage	INx, PGx, ENx⁽³⁾	–0.3	7.0	V
	INx, PGx, ENx (5% duty cycle, pulse duration = 200 µs)	–0.3	7.5
	OUTx	–0.3	V_INx + 0.3⁽²⁾
	SS_CTRLx	–0.3	V_INx + 0.3⁽²⁾
	NR/SSx, FBx⁽³⁾	–0.3	3.6
Current	OUTx⁽³⁾	Internally limited		A
Current	PGx (sink current into device)⁽³⁾		5	mA
Temperature	Operating junction, T_J	–55	150	°C
Temperature	Storage, T_stg	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The absolute maximum rating is V_INx + 0.3 V or 7.0 V, whichever is smaller.

(3) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2, one channel at a time.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_INx	Input supply voltage range	1.4	6.5	V
V_OUTx	Output voltage range	0.8 – 1%	5.2 + 1%	V
I_OUTx	Output current	0	2	A
C_INx	Input capacitor, each input	10		µF
C_OUTx	Output capacitor	22		µF
C_NR/SSx	Noise-reduction capacitor		1	µF
R_PGx	Power-good pullup resistance	10	100	kΩ
T_J	Junction temperature range	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS7A89	UNIT
		RTJ (WQFN)
		20 PINS
R_θJA	Junction-to-ambient thermal resistance	33	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	26.8	°C/W
R_θJB	Junction-to-board thermal resistance	8.0	°C/W
ψ_JT	Junction-to-top characterization parameter	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter	8.0	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.4	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

over operating temperature range (T_J = –40°C to +125°C), V_INx = 1.4 V or V_OUT_x_(TARGET)+ 0.2 V (whichever is greater), V_OUTx(TARGET) = 0.8 V, I_OUTx = 50 mA, V_ENx = 1.4 V, C_OUTx = 10 μF, C_NR/SSx = 0 nF, C_FFx = 0 nF, SS_CTRLx = GND, PGx pin pulled up to V_INx with 100 kΩ, and for each channel (unless otherwise noted); typical values are at T_J = 25°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_INx⁽²⁾	Input supply voltage range		1.4		6.5	V
V_REF	Reference voltage			0.8		V
V_UVLOx	Input supply UVLOx	V_INx rising		1.31	1.39	V
V_UVLOx(HYS)	V_UVLOx hysteresis	V_INx falling hysteresis		290		mV
V_OUTx	Output voltage range		0.8 – 1%		5.2 + 1%	V
	V_OUTx accuracy⁽¹⁾	0.8 V ≤ V_OUTx ≤ 5.2 V, 5 mA ≤ I_OUTx ≤ 2 A	–1.0%		1.0%
ΔV_OUTx(ΔVINx)	Line regulation	I_OUTx = 5 mA, 1.4 V ≤ V_INx ≤ 6.5 V		0.003		%/V
ΔV_{OUTx(ΔIOUTx)}	Load regulation	5 mA ≤ I_OUTx ≤ 2 A		0.03		%/A
V_OSx	Error amplifier offset voltage	T_J = 25°C	–2		2	mV
V_OS1 – V_OS2	Delta between each channel offset voltage	T_J = 25°C	–2		2	mV
V_DO	Dropout voltage	1.8 V ≤ V_INx ≤ 4.8 V, I_OUTx = 2 A, V_FBx = 0.8 V – 3%		180	300	mV
V_DO	Dropout voltage	1.4 V ≤ V_INx < 1.8 V and 4.8 V < V_INx ≤ 5.6 V, I_OUTx = 2 A, V_FBx = 0.8 V – 3%		250	400	mV
I_LIM	Output current limit	V_OUTx forced at 0.9 × V_OUTx(TARGET)	2.3	2.6	2.9	A
I_GND	GND pin current	Both channels enabled, per channel, V_INx = 6.5 V, I_OUTx = 5 mA		2.1	3.5	mA
I_GND	GND pin current	Both channels enabled, per channel, V_INx = 1.4 V, I_OUTx = 2 A			4	mA
I_SDN	Shutdown GND pin current	Both channels shutdown, per channel, PGx = (open), V_INx = 6.5 V, V_ENx = 0.4 V		0.1	15	μA
I_ENx	ENx pin current	V_INx = 6.5 V, 0 V ≤ V_ENx ≤ 6.5 V	–0.2		0.2	μA
V_IL(ENx)	ENx pin low-level input voltage (device disabled)		0		0.4	V
V_IH(ENx)	ENx pin high-level input voltage (device enabled)		1.1		6.5	V
I_{SS_CTRLx}	SS_CTRLx pin current	V_INx = 6.5 V, 0 V ≤ V_{SS_CTRLx} ≤ 6.5 V	–0.2		0.2	μA
V_IT(PGx)	PGx pin threshold	For PGx transitioning low with falling V_OUTx, expressed as a percentage of V_OUTx(TARGET)	82%	88.9%	93%
V_hys(PGx)	PGx pin hysteresis	For PGx transitioning high with rising V_OUTx, expressed as a percentage of V_OUTx(TARGET)		1%
V_OL(PGx)	PGx pin low-level output voltage	V_OUTx < V_IT(PGx), I_PGx = –1 mA (current into device)			0.4	V
I_lkg(PGx)	PGx pin leakage current	V_OUTx > V_IT(PGx), V_PGx = 6.5 V			1	µA
I_NR/SSx	NR/SSx pin charging current	V_NR/SSx = GND, 1.4 V ≤ V_INx ≤ 6.5 V, V_{SS_CTRLx} = GND	4.0	6.2	9.0	µA
I_NR/SSx	NR/SSx pin charging current	V_NR/SSx = GND, 1.4 V ≤ V_INx ≤ 6.5 V, V_{SS_CTRLx} = V_INx	65	100	150	µA
I_FBx	FBx pin leakage current	V_INx = 6.5 V, V_FBx = 0.8 V	–100		100	nA
PSRR	Power-supply rejection ratio	f = 500 kHz, V_INx = 3.8 V, V_OUTx = 3.3 V, I_OUTx = 250 mA, C_NR/SSx = 10 nF, C_FFx = 10 nF		40		dB
V_n	Output noise voltage	BW = 10 Hz to 100 kHz, V_INx = 1.8 V, V_OUTx = 0.8 V, I_OUTx = 1 A, C_NR/SSx = 1 µF, C_FFx = 100 nF		3.8		μV_RMS
	Noise spectral density	f = 10 kHz, V_INx = 1.8 V, V_OUTx = 0.8 V, I_OUTx = 1 A, C_NR/SSx = 10 nF, C_FFx = 10 nF		11		nV/√Hz
R_diss	Output active discharge resistance	V_ENx = GND		250		Ω
T_sdx	Thermal shutdown temperature	Shutdown, temperature increasing		160		°C
T_sdx	Thermal shutdown temperature	Reset, temperature decreasing		140		°C

(1) When the device is connected to external feedback resistors at the FBx pins, external resistor tolerances are not included.

(2) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2.

6.6 Typical Characteristics

at T_J = 25°C, 1.4 V ≤ V_INx < 6.5 V, V_INx ≥ V_OUTx(TARGET) + 0.3 V, V_OUTx = 0.8 V, SS_CTRLx = GND, I_OUTx = 5 mA, V_ENx = 1.1 V, C_OUTx = 22 μF, C_NR/SSx = 0 nF, C_FFx = 0 nF, PGx pin pulled up to V_OUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise noted)

TPS7A89 tc_PSRR_vs_Cnrss_5p5Vin_5Vout_2A.gif

V_OUTx = 5 V, V_INx = 5.5 V, V_ENx = V_INx, I_OUTx = 2 A,
C_OUTx = 22 µF, C_FFx = 10 nF

Figure 1. Power-Supply Rejection Ratio vs
Frequency and C_NR/SSx

V_OUTx = 5 V, V_INx = 5.4 V, V_ENx = V_INx,
C_OUTx = 22 µF, C_NR/SSx = C_FFx = 10 nF

Figure 3. Power-Supply Rejection Ratio vs
Frequency and Output Current

V_INx = V_OUTx + 0.4 V, I_OUTx = 2.0 A, C_OUTx = 22 µF,
C_NR/SSx = C_FFx = 10 nF

Figure 5. Power-Supply Rejection Ratio vs
Frequency and Output Voltage

V_OUTx = 1.8 V, I_OUTx = 100 mA, C_OUTx = 22 µF,
C_NR/SSx = C_FFx = 10 nF

Figure 7. Channel-to-Channel Output Voltage Isolation vs Frequency

I_OUTx = 2 A, V_INx = 5.5 V

Figure 9. Output Noise at V_OUTx= 5 V

V_INx = 1.7 V, V_OUTx = 1.2 V, I_OUTx = 1 A, V_RMS BW = 22 Hz to 100 kHz, C_OUTx = 10 µF, C_FFx = 10 nF

Figure 11. Noise vs Frequency and C_NR/SSx

V_OUTx = 1.2 V, I_OUTx = 1 A, C_OUTx = 22 µF, C_NR/SSx = 10 nF

Figure 13. Noise vs Frequency and V_INx

V_OUTx = 1.8 V, I_OUTx = 1 A, C_OUTx = 22 µF, C_NR/SSx = 1 µF,
BW = 10 Hz to 100 kHz

Figure 15. RMS Output Noise vs C_FFx

V_INx = 5.5 V, V_OUTx= 5 V, C_OUTx = 22 µF, C_FFx = C_NR/SSx = 10 nF, slew rate = 1 A/µs

Figure 17. Load Transient Response vs DC Load

TPS7A89 tc_Load_Trans_vs_SR_5Vout_100mA_2A.gif

V_INx = 5.5 V, V_OUTx= 5 V, I_OUTx = 100 mA to 2 A, C_OUTx = 22 µF, C_FFx = C_NR/SSx = 10 nF

Figure 19. Load Transient Response vs Slew Rate

Figure 21. Dropout Voltage vs Output Current

Figure 23. Dropout Voltage vs Junction Temperature

I_OUTx = 50 mA

Figure 25. Line Regulation (V_OUTx = 0.8 V)

I_OUTx = 5 mA

Figure 27. Line Regulation (V_OUTx = 3.3 V)

Single Channel

Figure 29. Shutdown Current vs Input Voltage

Single Channel

Figure 31. Ground Current vs Input Voltage

Figure 33. PGx Low Level vs PGx Current (V_INx = 6.5 V)

V_INx = V_PGx = 6.5 V

Figure 35. PGx Leakage Current vs Temperature

Figure 37. Enable Threshold vs Temperature

V_INx = 1.4 V to 6.5 V to 1.4 V at 2 V/µs, V_OUTx = 0.8 V,
I_OUTx = 1 A, C_NR/SSx = C_FFx = 10 nF

Figure 39. Line Transient

V_INx = 1.4 V

Figure 41. Start-Up (SS_CTRLx = GND, C_NR/SSx = 10 nF)

V_INx = 1.4 V

Figure 43. Start-Up (SS_CTRLx = V_INx, C_NR/SSx = 1 µF)

V_OUTx = 5 V, I_OUTx = 2 A, C_OUTx = 22 µF,
C_NR/SSx = C_FFx = 10 nF

Figure 2. Power-Supply Rejection Ratio vs
Frequency and Input Voltage

TPS7A89 tc_PSRR_vs_Cout_5Vout_5p5Vin_2A.gif

V_OUTx = 5.0 V, V_INx = 5.5 V, V_ENx = V_INx, I_OUTx = 2 A,
C_OUTx = ceramic, C_NR/SSx = C_FFx = 10 nF

Figure 4. Power-Supply Rejection Ratio vs
Frequency and Output Capacitance

TPS7A89 tc_PSRR_vs_Caps_5p5Vin_5Vout_2A.gif

I_OUTx = 2 A, V_INx = 5.5 V

Figure 6. Power-Supply Rejection Ratio at V_OUTx = 5.0 V

V_INx = V_OUTx + V_DOx(max) + 0.1 V or 1.4 V (whichever is greater), I_OUTx = 2 A

Figure 8. Output Noise vs Output Voltage

V_INx = V_OUTx + 1.0 V, I_OUTx = 1 A, V_RMS BW = 22 Hz to 100 kHz, C_OUTx = 10 µF, C_NR/SSx = C_FFx = 10 nF

Figure 10. Noise vs Frequency and Output Voltage

V_INx = 3.8 V, V_OUTx = 3.3 V, I_OUTx = 1 A, V_RMS BW = 22 Hz to 100 kHz, C_OUTx = 10 µF, C_NR/SSx = 10 nF

Figure 12. Noise vs Frequency and C_FFx

V_OUTx = 1.8 V, I_OUTx = 1 A, C_OUTx = 22 µF, C_FFx = 0.01 µF,
BW = 10 Hz to 100 kHz

Figure 14. RMS Output Noise vs C_NR/SSx

TPS7A89 tc_Load_Trans_vs_Vout_100mA_2A_1Aus.gif

V_INx = V_OUTx + 0.5 V, I_OUTx = 100 mA to 2 A, C_OUTx = 22 µF,
C_FFx = C_NR/SSx = 10 nF, slew rate = 1 A/µs

Figure 16. Load Transient Response vs V_OUTx

TPS7A89 tc_Load_Trans_vs_Cout_1mA_2A_1Aus.gif

V_INx = 5.5 V, V_OUTx= 5 V, I_OUTx = 100 mA to 2 A, C_FFx = C_NR/SSx = 10 nF, slew rate = 1 A/µs

Figure 18. Load Transient Response vs Output Capacitor

V_INx = 1.4 V, V_OUTx = 0.8 V

Figure 20. Current Limit Foldback

Figure 22. Dropout Voltage vs Input Voltage

Figure 24. Load Regulation (V_OUTx = 1.2 V)

V_INx = 3.8 V

Figure 26. Load Regulation (V_OUTx = 3.3 V)

V_INx = 5.5 V

Figure 28. Load Regulation (V_OUTx = 5.0 V)

V_INx = 1.4 V, Single Channel

Figure 30. Ground Current vs Output Current

Figure 32. PGx Low Level vs PGx Current (V_INx = 1.4 V)

Figure 34. PGx Threshold vs Temperature

Figure 36. Soft-Start Current vs Temperature
(SS_CTRLx = GND)

Figure 38. Input UVLOx Threshold vs Temperature

V_INx = 1.4 V

Figure 40. Start-Up (SS_CTRLx = GND, C_NR/SSx = 0 nF)

V_INx = 1.4 V

Figure 42. Start-Up (SS_CTRLx = V_INx, C_NR/SSx = 10 nF)