ZHCSJP1B May 2019 – October 2022 TPS65987DDJ
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Supply Requirements and Characteristics
- 6.6 Power Consumption Characteristics
- 6.7 Power Switch Characteristics
- 6.8 Cable Detection Characteristics
- 6.9 USB-PD Baseband Signal Requirements and Characteristics
- 6.10 BC1.2 Characteristics
- 6.11 Thermal Shutdown Characteristics
- 6.12 Oscillator Characteristics
- 6.13 I/O Characteristics
- 6.14 I2C Requirements and Characteristics
- 6.15 SPI Controller Timing Requirements
- 6.16 HPD Timing Requirements
- 6.17 Typical Characteristics
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 USB-PD Physical Layer
- 8.3.2 Power Management
- 8.3.3 Port Power Switches
- 8.3.4 Cable Plug and Orientation Detection
- 8.3.5 Dead Battery Operation
- 8.3.6 Battery Charger Detection and Advertisement
- 8.3.7 ADC
- 8.3.8 DisplayPort HPD
- 8.3.9 Digital Interfaces
- 8.3.10 Digital Core
- 8.3.11 I2C Interfaces
- 8.3.12 SPI Controller Interface
- 8.3.13 Thermal Shutdown
- 8.3.14 Oscillators
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Applications
- 9.2.1 Type-C VBUS Design Considerations
- 9.2.2 Notebook Design Supporting PD Charging
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSH|56
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSH|56
訂購信息
11.5 Routing CC and GPIO
Routing the CC lines with a 8-mil trace will ensure the needed current for supporting powered Type-C cables through VCONN. For more information on VCONN refer to the Type-C specification. For capacitor GND pin use a 16-mil trace if possible.
Most of the GPIO signals can be fanned out on the top layer with a 4-mil trace. The PP_EXT1/2 GPIO control go through a via to be routed on another layer.
Figure 11-10 below shows the CC and GPIO routing.
Figure 11-10 CC Routing and GPIO Fan-OutTable 11-1 Routing Widths
| ROUTE | WIDTH (mil minimum) |
|---|---|
| CC1, CC2, PP_CABLE1, PP_CABLE2 | 8 |
| VIN_3V3, LDO_3V3, LDO_1V8 | 6 |
| Component GND | 10 |
| GPIO | 4 |