ZHCSEL9B december 2015 – may 2023 TPS65265
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Adjusting the Output Voltage
- 8.3.2 Mix PGOOD, PG_DLY Functions
- 8.3.3 Enable and Adjusting UVLO
- 8.3.4 Soft-Start Time
- 8.3.5 Power-Up Sequencing
- 8.3.6 V7V Low Dropout Regulator and Bootstrap
- 8.3.7 Out of Phase Operation
- 8.3.8 Output Overvoltage Protection (OVP)
- 8.3.9 PSM
- 8.3.10 Slope Compensation
- 8.3.11 Overcurrent Protection
- 8.3.12 Adjustable Switching Frequency
- 8.3.13 Thermal Shutdown
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
訂購信息
8.3.2.1 Programmable PGOOD DELAY
An internal 3-μA pullup current source is connected to PG_DLY pin. The PGOOD delay time can be programmed by connecting a capacitor between PG_DLY pin and ground. The delay time can be calculated as Equation 2.
Equation 2. 
where
- VPG_DLY = 1.5 V
- Ip = 3 μA
Figure 8-2 Power Good Delay Timing Diagram