ZHCSG04F january 2017 – may 2023 TPS65235-1
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Boost Converter
- 7.3.2 Linear Regulator and Current Limit
- 7.3.3 Boost Converter Current Limit
- 7.3.4 Charge Pump
- 7.3.5 Slew Rate Control
- 7.3.6 Short-Circuit Protection, Hiccup, and Overtemperature Protection
- 7.3.7 Tone Generation
- 7.3.8 Tone Detection
- 7.3.9 Audio Noise Rejection
- 7.3.10 Disable and Enable
- 7.3.11 Component Selection
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RUK|20
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RUK|20
訂購信息
7.3.11.2 Capacitor Selection
The TPS65235-1 device has a 1-MHz nonsynchronous boost converter integrated and the boost converter features the internal compensation network. The TPS65235-1 device works well with both ceramic capacitor and electrolytic capacitor.
The recommended ceramic capacitors for the TPS65235-1 application are, at the minimum, rated as X7R/X5R, with a 35-V rating, and a 1206 size for the achieving lower LNB output ripple. Table 7-1 lists the recommended ceramic capacitors list for both 4.7-μH and 10-μH boost inductors.
If more cost-effictive design is needed, use a 100-μF electrolytic (low ESR) and a 10-μF or 35-V ceramic capacitor.
| BOOST INDUCTOR | CAPACITORS | TOLERANCE (%) | RATING (V) | SIZE |
|---|---|---|---|---|
| 10 μH | 2 × 22 μF | ±10 | 35 | 1206 |
| 2 × 10 μF | ±10 | 35 | 1206 | |
| 4.7 μH | 2 × 22 μF | ±10 | 35 | 1206 |
| 2 × 10 μF | ±10 | 35 | 1206 | |
| 22 μF | ±10 | 35 | 1206 |
Figure 7-6 and Figure 7-7 show a bode plot of boost loop with 4.7-μH and 10-μH inductance and 4 μF, 5 μF, 7.5 μF, 10 μF, 15 μF, and 20 μF of boost capacitance after degrading. As the boost capacitance increases, the phase margin increases.
Figure 7-6 Gain and Phase Margin of the Boost Loop With Different Boost Capacitance (VIN = 12 V, VOUT = 18.2 V, ILOAD = 1 A, fSW = 1 MHz, 4.7 μH, Typical Bode Plot)
Figure 7-7 Gain and Phase Margin of
the Boost Loop With Different Boost Capacitance (VIN = 12 V,
VOUT = 18.2 V, ILOAD = 1 A,
fSW = 1 MHz, 10 μH, Typical Bode Plot)