ZHCSI59I July 2009 – May 2018 TPS65070 , TPS65072 , TPS65073 , TPS650731 , TPS650732
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
TPS6507x contains a sequencing option for the Sirf Prima processor. The sequencing option defines how the voltages are ramped at initial power-up and shutdown as well as the timing for entering power save mode for the processor (SLEEP mode). The Prima processor supports SLEEP mode and also DEEP SLEEP mode. The main difference from a power supply point of view is:
The sequencing option for Prima is defined in one register each for the sequencing of the DC-DC converters and for the LDOs. DCDC_SQ[2..0]=100 in register CON_CTRL1 defines the start-up sequence for the DC-DC converters while LDO_SQ[2..0]=111 defines the sequence for the LDOs. The default is factory programmed therefore it is ensured the first power-up is done in the right sequence.
When TPS6507x is off, a small state machine supervises the status of pin PB_IN while major blocks are not powered for minimum current consumption from the battery as long as there is no input voltage to the charger. Power-up for the TPS6507x is started by PB_IN going LOW. This will turn on the power-FET from the battery so the system voltage (SYS) is rising and the main blocks of the PMU are powered. After a debounce time of 50 ms, the main state machine will pull PB_OUT = LOW to indicate that there is a “keypress” by the user and will ramp the DC-DC converters and LDOs according to the sequence programmed. It is important to connect the power rails for the processor to exactly the DC-DC converters and LDOs as shown in the schematic and sequencing diagrams for proper sequencing. For Prima, the voltage rails for VDD_RTCIO needs to ramp first. This power rail is not provided by the PMU but from an external LDO which is enabled by a signal called EN_EXTLDO from the PMU. The PMU will therefore first rise the logic level an pin EN_EXTLDO high to enable the external LDO. After a 1-ms delay the PMU will ramp LDO2 for VDD_PRE and DCDC3 for VDD_PDN. When the output voltage of LDO2 is within it s nominal range the internal power good comparator will trigger the state machine which will ramp DCDC1 and DCDC2 to provide the supply voltage for VCC_3V3 and VCC_1V8. Now Prima needs to pull its X_PWR_EN signal high which drives EN_DCDC3 on the PMU. This will now enable LDO1 to power VDDPLL. X_RESET_B will be released by the PMU on pin PGOOD based on the voltage of DCDC1 after a delay of 20 ms.