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ZHCSE52B September 2015 – May 2019 TPS57140-EP

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DRC|10
- MPDS117L

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

DRC|10
- QFND013N

訂購信息

6.5 Electrical Characteristics

T_J = –55°C to 150°C, VIN = 3.5 to 42 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (VIN PIN)
	Operating input voltage		3.5		42	V
	Internal UVLO threshold	No voltage hysteresis, rising and falling		2.5		V
	Shutdown supply current	EN = 0 V, 25°C, 3.5 V ≤ V_IN ≤ 60 V		1.5	4	μA
	Shutdown supply current	EN = 0 V, 125°C, 3.5 V ≤ V_IN ≤ 60 V		1.9	6.5
	Operating: nonswitching supply current	V_SENSE = 0.83 V, V_IN = 12 V, 25°C		116	140
ENABLE AND UVLO (EN PIN)
	Enable threshold voltage	No voltage hysteresis, rising and falling, 25°C	1.15	1.25	1.36	V
	Input current	Enable threshold 50 mV		–3.8		μA
	Input current	Enable threshold –50 mV		–0.9		μA
	Hysteresis current			–2.9		μA
VOLTAGE REFERENCE
	Voltage reference	T_J = 25°C	0.790	0.8	0.808	V
	Voltage reference		0.780	0.8	0.819	V
HIGH-SIDE MOSFET
	On-resistance	V_IN = 3.5 V, BOOT-PH = 3 V		300		mΩ
	On-resistance	V_IN = 12 V, BOOT-PH = 6 V		200	410	mΩ
ERROR AMPLIFIER
	Input current			50		nA
	Error amplifier transconductance (gm)	–2 μA < I_COMP < 2 μA, V_COMP = 1 V		97		μS
	Error amplifier transconductance (gm) during slow start	–2 μA < I_COMP < 2 μA, V_COMP = 1 V, V_VSENSE = 0.4 V		26		μS
	Error amplifier dc gain	V_VSENSE = 0.8 V		10 000		V/V
	Error amplifier bandwidth			2700		kHz
	Error amplifier source/sink	V_(COMP) = 1 V, 100-mV overdrive		±7		μA
	COMP to switch current transconductance			6		S
CURRENT LIMIT
	Current-limit threshold	V_IN = 12 V, T_J = 25°C	1.8	2.7		A
THERMAL SHUTDOWN
	Thermal shutdown			182		°C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
	Switching-frequency range using RT mode	V_IN = 12 V	100		2500	kHz
f_SW	Switching frequency	V_IN = 12 V, R_T = 200 kΩ	450	581	720	kHz
	Switching-frequency range using CLK mode	V_IN = 12 V	300		2200	kHz
	Minimum CLK pulse duration			40		ns
	RT/CLK high threshold	V_IN = 12 V		1.9	2.2	V
	RT/CLK low threshold	V_IN = 12 V	0.45	0.7		V
	RT/CLK falling-edge to PH rising-edge delay	Measured at 500 kHz with RT resistor in series		60		ns
	PLL lock in time	Measured at 500 kHz		100		μs
SLOW START AND TRACKING (SS/TR)
	Charge current	V_SS/TR = 0.4 V		2		μA
	SS/TR-to-VSENSE matching	V_SS/TR = 0.4 V		45		mV
	SS/TR-to-reference crossover	98% nominal		1		V
	SS/TR discharge current (overload)	V_SENSE = 0 V, V_(SS/TR) = 0.4 V		112		μA
	SS/TR discharge voltage	V_SENSE = 0 V		54		mV
POWER GOOD (PWRGD PIN)
V_VSENSE	VSENSE threshold	V_SENSE falling		92%
		V_SENSE rising		94%
		V_SENSE rising		109%
		V_SENSE falling		107%
	Hysteresis	V_SENSE falling		2%
	Output-high leakage	V_SENSE = V_REF, V_(PWRGD) = 5.5 V, 25°C		10		nA
	On-resistance	I_(PWRGD) = 3 mA, V_SENSE < 0.79 V		50		Ω
	Minimum VIN for defined output	V_(PWRGD) < 0.5 V, I_I(PWRGD) = 100 μA		0.95	1.5	V

1. Electromigration fail mode = Time at temperature with bias

2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).

3. The predicted operating lifetime versus junction temperature is based on reliability modeling and available qualification data.

Figure 1. Predicted Lifetime Derating Chart for TPS57140-EP