ZHCSNR7A March 2022 – August 2022 TPS55289
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| I2C TIMING | ||||||
| fSCL | SCL clock frequency | 100 | 1000 | kHz | ||
| tBUF | Bus free time between a STOP and START condition | Fast mode plus | 0.5 | μs | ||
| tHD(STA) | Hold time (repeated) START condition | 260 | ns | |||
| tLOW | Low period of the SCL clock | 0.5 | μs | |||
| tHIGH | High period of the SCL clock | 260 | ns | |||
| tSU(STA) | Setup time for a repeated START condition | 260 | ns | |||
| tSU(DAT) | Data setup time | 50 | ns | |||
| tHD(DAT) | Data hold time | 0 | μs | |||
| tRCL | Rise time of SCL signal | 120 | ns | |||
| tRCL1 | Rise time of SCL signal after a repeated START condition and after an ACK bit | 120 | ns | |||
| tFCL | Fall time of SCL signal | 120 | ns | |||
| tRDA | Rise time of SDA signal | 120 | ns | |||
| tFDA | Fall time of SDA signal | 120 | ns | |||
| tSU(STO) | Setup time of STOP condition | 260 | ns | |||
| CB | Capacitive load for SDA and SCL | 200 | pF | |||