ZHCSFC5A August 2016 – September 2017 TPS549D22
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 Programmable Pin-Strap Settings
- 7.5.2 Programmable Analog Configurations
- 7.5.3 PMBus Programming
- 7.5.4
Register Maps
- 7.5.4.1 OPERATION Register (address = 1h)
- 7.5.4.2 ON_OFF_CONFIG Register (address = 2h)
- 7.5.4.3 CLEAR FAULTS (address = 3h)
- 7.5.4.4 WRITE PROTECT (address = 10h)
- 7.5.4.5 STORE_DEFAULT_ALL (address = 11h)
- 7.5.4.6 RESTORE_DEFAULT_ALL (address = 12h)
- 7.5.4.7 CAPABILITY (address = 19h)
- 7.5.4.8 VOUT_MODE (address = 20h)
- 7.5.4.9 VOUT_COMMAND (address = 21h)
- 7.5.4.10 VOUT_MARGIN_HIGH (address = 25h)
- 7.5.4.11 VOUT_MARGIN_LOW (address = 26h)
- 7.5.4.12 STATUS_BYTE (address = 78h)
- 7.5.4.13 STATUS_WORD (High Byte) (address = 79h)
- 7.5.4.14 STATUS_VOUT (address = 7Ah)
- 7.5.4.15 STATUS_IOUT (address = 7Bh)
- 7.5.4.16 STATUS_CML (address = 7Eh)
- 7.5.4.17 MFR_SPECIFIC_00 (address = D0h)
- 7.5.4.18 MFR_SPECIFIC_01 (address = D1h)
- 7.5.4.19 MFR_SPECIFIC_02 (address = D2h)
- 7.5.4.20 MFR_SPECIFIC_03 (address = D3h)
- 7.5.4.21 MFR_SPECIFIC_04 (address = D4h)
- 7.5.4.22 MFR_SPECIFIC_06 (address = D6h)
- 7.5.4.23 MFR_SPECIFIC_07 (address = D7h)
- 7.5.4.24 MFR_SPECIFIC_44 (address = FCh)
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application: TPS549D22 1.5-V to 16-V Input, 1-V Output, 40-A Converter
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Custom Design With WEBENCH® Tools
- 8.2.2.2 Switching Frequency Selection
- 8.2.2.3 Inductor Selection
- 8.2.2.4 Output Capacitor Selection
- 8.2.2.5 Input Capacitor Selection
- 8.2.2.6 Bootstrap Capacitor Selection
- 8.2.2.7 BP Pin
- 8.2.2.8 R-C Snubber and VIN Pin High-Frequency Bypass
- 8.2.2.9 Optimize Reference Voltage (VSEL)
- 8.2.2.10 MODE Pin Selection
- 8.2.2.11 ADDR Pin Selection
- 8.2.2.12 Overcurrent Limit Design
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RVF|40
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RVF|40
訂購信息
7 Detailed Description
7.1 Overview
TPS549D22 device is a high-efficiency, single channel, FET-integrated, synchronous buck converter. It is suitable for point-of-load applications with 40 A or lower output current in storage, telecom, and similar digital applications. The device features proprietary D-CAP3 mode control combined with adaptive on-time architecture. This combination is ideal for building modern high/low duty ratio, ultra-fast load step response DC-DC converters.
TPS549D22 device has integrated MOSFETs rated at 40-A TDC.
The converter input voltage range is from 1.5 V up to 16 V, and the VDD input voltage range is from 4.5 V to 22 V. The output voltage ranges from 0.6 V to 5.5 V.
Stable operation with all ceramic output capacitors is supported, since the D-CAP3 mode uses emulated current information to control the modulation. An advantage of this control scheme is that it does not require phase compensation network outside which makes it easy to use and also enables low external component count. Adaptive on-time control tracks the preset switching frequency over a wide range of input and output voltage while increasing switching frequency as needed during load-step transient.
The default preset switching frequency for this device is 650 kHz. Switching frequency is also programmable from 8 preset values via PMBus interface. TPS549D22 supports digital communication via PMBus using standard interfacing pins, PMB_CLK, PMB_DATA and SMB_ALRT#. The detailed PMBus features, capabilities and command sets of the TPS549D22 can be found in the PMBus Programming section.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 40-A FET
The TPS549D22 device is a high-performance, integrated FET converter supporting current rating up to 40 A thermally. It integrates two N-channel NexFET™ power MOSFETs, enabling high power density and small PCB layout area. The drain-to-source breakdown voltage for these FETs is 25 V DC and 27 V transient for 10 ns. Avalanche breakdown occurs if the absolute maximum voltage rating exceeds 27 V. In order to limit the switch node ringing of the device, it is recommended to add a R-C snubber from the SW node to the PGND pins. Refer to the Layout Guidelines section for the detailed recommendations.
7.3.2 On-Resistance
The typical on-resistance (RDS(on)) for the high-side MOSFET is 2.9 mΩ and typical on-resistance for the low-side MOSFET is 1.2 mΩ with a nominal gate voltage (VGS) of 5 V.
7.3.3 Package Size, Efficiency and Thermal Performance
The TPS549D22 device is available in a 7 mm × 5 mm, LQFN-CLIP package with 40 power and I/O pins. It employs TI proprietary MCM packaging technology with thermal pad. With a properly designed system layout, applications achieve optimized safe operating area (SOA) performance. The curves shown in Figure 23 and Figure 24 are based on the orderable evaluation module design. (See SLUUBG4 to order the EVM).
7.3.4 Soft-Start Operation
In the TPS549D22 device the soft-start time controls the inrush current required to charge the output capacitor bank during startup. The device offers selectable soft-start options of 1 ms, 2 ms, 4 ms and 8 ms. When the device is enabled (either by EN or VDD UVLO), the reference voltage ramps from 0 V to the final level defined by VSEL pin strap configuration, in a given soft-start time. The TPS549D22 device supports several soft-start times between 1msec and 8msec selected by MODE pin configuration. Refer to MODE definition table for details.
7.3.5 VDD Supply Undervoltage Lockout (UVLO) Protection
The TPS549D22 device provides fixed VDD undervoltage lockout threshold and hysteresis. The typical VDD turn-on threshold is 4.25 V and hysteresis is 0.2 V. The VDD UVLO can be used in conjunction with the EN_UVLO signal to provide proper power sequence to the converter design. UVLO is a non-latched protection.
7.3.6 EN_UVLO Pin Functionality
The EN_UVLO pin drives an input buffer with accurate threshold and can be used to program the exact required turn-on and turn-off thresholds for switcher enable, VDD UVLO or VIN UVLO (if VIN and VDD are tied together). If desired, an external resistor divider can be used to set and program the turn-on threshold for VDD or VIN UVLO.
Figure 25 shows how to program the input voltage UVLO using the EN_UVLO pin.
Figure 25. Programming the UVLO Voltage
7.3.7 Fault Protections
This section describes positive and negative overcurrent limits, overvoltage protections, out-of-bounds limits, undervoltage protections and over temperature protections.
7.3.7.1 Current Limit (ILIM) Functionality
Figure 26. Current Limit Resistance vs OCP Valley Overcurrent Limit
The ILIM pin sets the OCP level. Connect the ILIM pin to GND through the voltage setting resistor, RILIM. In order to provide both good accuracy and cost effective solution, TPS549D22 device supports temperature compensated internal MOSFET RDS(on) sensing.
Also, the TPS549D22 device performs both positive and negative inductor current limiting with the same magnitudes. The positive current limit normally protects the inductor from saturation that causes damage to the high-side FET and low-side FET. The negative current limit protects the low-side FET during OVP discharge.
The voltage between GND pin and SW pin during the OFF time monitors the inductor current. The current limit has 3000 ppm/°C temperature slope to compensate the temperature dependency of the on-resistance (RDS(on)). The GND pin is used as the positive current sensing node.
TPS549D22 device uses cycle-by-cycle over-current limiting control. The inductor current is monitored during the OFF state and the controller maintains the OFF state during the period that the inductor current is larger than the overcurrent ILIM level. VILIM sets the valley level of the inductor current.
7.3.7.2 VDD Undervoltage Lockout (UVLO)
The TPS549D22 device has an UVLO protection function for the VDD supply input. The on-threshold voltage is 4.25 V with 200 mV of hysteresis. During a UVLO condition, the device is disabled regardless of the EN_UVLO pin voltage. The supply voltage (VVDD) must be above the on-threshold to begin the pin strap detection.
7.3.7.3 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
The device monitors a feedback voltage to detect overvoltage and undervoltage. When the feedback voltage becomes lower than 68% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 1 ms, the device latches OFF both high-side and low-side MOSFETs drivers. The UVP function enables after soft-start is complete.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side FET is turned on again for a minimum on-time. The TPS549D22 device operates in this cycle until the output voltage is pulled down under the UVP threshold voltage for 1 ms. After the 1-ms UVP delay time, the high-side FET is latched off and low-side FET is latched on. The fault is cleared with a reset of VDD or by retoggling the EN pin.
Table 1. Overvoltage Protection Details
| REFERENCE VOLTAGE (VREF) |
SOFT-START RAMP | STARTUP OVP THRESHOLD | OPERATING OVP THRESHOLD | OVP DELAY 100 mV OD (µs) |
OVP RESET |
|---|---|---|---|---|---|
| Internal | Internal | 1.2 × Internal VREF | 1.2 × Internal VREF | 1 | UVP |
7.3.7.4 Out-of-Bounds Operation
The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, so the device is not latched off after an OOB event. OOB protection operates as an early no-fault overvoltage-protection mechanism. During the OOB operation, the controller operates in forced PWM mode only by turning on the low-side FET. Turning on the low-side FET beyond the zero inductor current quickly discharges the output capacitor thus causing the output voltage to fall quickly toward the setpoint. During the operation, the cycle-by-cycle negative current limit is also activated to ensure the safe operation of the internal FETs.
7.3.7.5 Overtemperature Protection
TPS549D22 device has overtemperature protection (OTP) by monitoring the die temperature. If the temperature exceeds the threshold value (default value 165°C), TPS549D22 device is shut off. When the temperature falls about 25°C below the threshold value, the device turns on again. The OTP is a non-latch protection.
7.4 Device Functional Modes
7.4.1 DCAP3 Control Topology
The TPS549D22 employs an artificial ramp generator that stabilizes the loop. The ramp amplitude is automatically adjusted as a function of selected switching frequency (fSW) The ramp amplitude is a function of duty cycle (VOUT-to-VIN ratio). Consequently, two additional pin-strap bits (ADDR[2:1]) are provided for fine tuning the internal ramp amplitude. The device uses an improved DCAP3 control loop architecture that incorporates a steady-state error integrator. The slow integrator improves the output voltage DC accuracy greatly and presents minimal impact to small signal transient response. To further enhance the small signal stability of the control loop, the device uses a modified ramp generator that supports a wider range of output LC stage.
7.4.2 DCAP Control Topology
For advanced users of this device, the internal DCAP3 ramp can be disabled using the MODE[4] pin strap bit. This situation requires an external RCC network to ensure control loop stability. Place this RCC network across the output inductor. Use a range between 10 mV and 15 mV of injected RSP pin ripple. If no feedback resistor divider network is used, insert a 10-kΩ resistor between the VOUT pin and the RSP pin.
7.5 Programming
7.5.1 Programmable Pin-Strap Settings
ADDR, VSEL and MODE. Description: a 1% or better 100-kΩ resistor is needed from BP to each of the three pins. The bottom resistor from each pin to ground (see MODE, VSEL, ADDR DETECTION section of the Electrical Characteristics table) in conjunction with the top resistor defines each pin strap selection. The pin detection checks for external resistor divider ratio during initial power up (VDD is brought down below approximately 3 V) when BP LDO output is at approximately 2.9 V.
7.5.1.1 Address Selection (ADDR) Pin
The TPS549D22 allows up to 16 different chip addresses for PMBus communication with the first 3 bits fixed as 001. The address selection process is defined by resistor divider ratio from BP pin to ADDR pin, and the address detection circuit will start to work only after the initial power up when VDD has risen above its UVLO threshold. lists all combinations of the address selections. The 1% or better tolerance resistors with typical temperature coefficient of ±100ppm/°C are recommended.
ADDR pin strap configuration also programs the light load conduction mode.
7.5.1.2 VSEL Pin
VSEL pin strap configuration is used to program initial boot voltage value, hiccup mode and latch off mode. The initial boot voltage is used to program the main loop voltage reference point. VSEL voltage settings provide TI designated discrete internal reference voltages. Table 2 lists internal reference voltage selections.
Table 2. Internal Reference Voltage Selections
| VSEL[4] | VSEL[3] | VSEL[2] | VSEL[1] | VSEL[0] | RVSEL (kΩ) (1) |
|---|---|---|---|---|---|
| 1111: 0.975 V | 1: Latch-Off | Open | |||
| 0: Hiccup | 187 | ||||
| 1110: 1.1992 V | 1: Latch-Off | 165 | |||
| 0: Hiccup | 147 | ||||
| 1101: 1.1504 V | 1: Latch-Off | 133 | |||
| 0: Hiccup | 121 | ||||
| 1100: 1.0996 V | 1: Latch-Off | 110 | |||
| 0: Hiccup | 100 | ||||
| 1011: 1.0508 V | 1: Latch-Off | 90.9 | |||
| 0: Hiccup | 82.5 | ||||
| 1010: 1.0000 V | 1: Latch-Off | 75 | |||
| 0: Hiccup | 68.1 | ||||
| 1001: 0.9492 V | 1: Latch-Off | 60.4 | |||
| 0: Hiccup | 53.6 | ||||
| 1000: 0.9023 V | 1: Latch-Off | 47.5 | |||
| 0: Hiccup | 42.2 | ||||
| 0111: 0.9004 V | 1: Latch-Off | 37.4 | |||
| 0: Hiccup | 33.2 | ||||
| 0110: 0.8496 V | 1: Latch-Off | 29.4 | |||
| 0: Hiccup | 25.5 | ||||
| 0101: 0.8008 V | 1: Latch-Off | 22.1 | |||
| 0: Hiccup | 19.1 | ||||
| 0100: 0.7500 V | 1: Latch-Off | 16.5 | |||
| 0: Hiccup | 14.3 | ||||
| 0011: 0.6992 V | 1: Latch-Off | 12.1 | |||
| 0: Hiccup | 10 | ||||
| 0010: 0.6504 V | 1: Latch-Off | 7.87 | |||
| 0: Hiccup | 6.19 | ||||
| 0001: 0.5996 V | 1: Latch-Off | 4.64 | |||
| 0: Hiccup | 3.16 | ||||
| 0000: 0.975 V | 1: Latch-Off | 1.78 | |||
| 0: Hiccup | 0 | ||||
7.5.1.3 DCAP3 Control and Mode Selection
The MODE pinstrap configuration programs the control topology and internal soft-start timing selections. The TPS549D22 device supports both DCAP3 and DCAP operation
MODE[4] selection bit is used to set the control topology. If MODE[4] bit is “0”, it selects DCAP operation. If MODE[4] bit is “1”, it selects DCAP3 operation.
MODE[1] and MODE[0] selection bits are used to set the internal soft-start timing
7.5.1.4 Application Workaround to Support 4-ms and 8-ms SS Settings
In order to properly design for 4-ms and 8-ms SS settings, additional application consideration is needed. The recommended application workaround to support the 4-ms and 8-ms soft-start settings is to ensure sufficient time delay between the VDD and EN_UVLO signals. The minimum delay between the rising maximum VDD_UVLO level and the minimum turnon threshold of EN_UVLO is at least TDELAY_MIN.
where
- K = 9 ms/V for SS setting of 4 ms
- K = 18 ms/V for SS setting of 8 ms
- VREF is the internal reference voltage programmed by VSEL pin strap
For example, if SS setting is 4 ms and VREF = 1 V, program the minimum delay at least 9 ms; if SS setting is 8 ms, the minimum delay should be programmed at least 18 ms. See Figure 27 and Figure 28 for detailed timing requirement. Because TPS549D22 is a PMBus device, the end user has the option of programming power-on delay (POD) as another workaround. Be sure to follow the same calculation to determine the required POD (see MFR_SPECIFIC_01 (address = D1h) and Table 25 for more information).
Figure 27. Proper Sequencing of VDD and EN_UVLO to Support the Use of 4-ms SS Setting
Figure 28. Minimum Delay Between VDD and EN_UVLO to Support the Use of 4-ms and 8-ms SS settings
The workaround/consideration described previously is not required for SS settings of 1 ms and 2 ms.
7.5.2 Programmable Analog Configurations
7.5.2.1 RSP/RSN Remote Sensing Functionality
RSP and RSN pins are used for remote sensing purpose. In the case where feedback resistors are required for output voltage programming, the RSP pin should be connected to the mid-point of the resistor divider and the RSN pin should always be connected to the load return. In the case where feedback resistors are not required as when the VSEL programs the output voltage set point, the RSP pin should be connected to the positive sensing point of the load and the RSN pin should always be connected to the load return.
RSP and RSN pins are extremely high-impedance input terminals of the true differential remote sense amplifier. The feedback resistor divider should use resistor values much less than 100 kΩ.
7.5.2.1.1 Output Differential Remote Sensing Amplifier
The examples in this section show simplified remote sensing circuitry where each example uses an internal reference of 1 V. Figure 29 shows remote sensing without feedback resistors, with an output voltage set point of 1 V. Figure 30 shows remote sensing using feedback resistors, with an output voltage set point of 5 V.
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Figure 29. Remote Sensing Without Feedback Resistors
Figure 30. Remote Sensing With Feedback Resistors
7.5.2.2 Power Good (PGOOD Pin) Functionality
The TPS549D22 device has power-good output that registers high when switcher output is within the target. The power-good function is activated after soft-start has finished. When the soft-start ramp reaches 300 mV above the internal reference voltage, SSend signal goes high to enable the PGOOD detection function. If the output voltage becomes within ±8% of the target value, internal comparators detect power-good state and the power good signal becomes high after a 1-ms programmable delay. If the output voltage goes outside of ±16% of the target value, the power good signal becomes low after two microsecond (2-µs) internal delay. The open-drain power-good output must be pulled up externally. The internal N-channel MOSFET does not pull down until the VDD supply is above 1.2 V.
7.5.3 PMBus Programming
TPS549D22 has seven internal custom user-accessible 8-bit registers. The PMBus interface has been designed for program flexibility, supporting direct format for write operation. Read operations are supported for both combined format and stop separated format. While there is no auto increment/decrement capability in the TPS549D22 PMBus logic, a tight software loop can be designed to randomly access the next register independent of which register was accessed first. The start and stop commands frame the data packet and the repeat start condition is allowed when necessary.
7.5.3.1 TPS549D22 Limitations to the PMBUS Specifications
TPS549D22 only recognizes seven bit addressing. This means TPS549D22 is not compatible with ten bit addressing and CBUS communication. The device can operate in standard mode (100 kbit/s), fast mode (400 kbit/s) or faster mode (1000 kbit/s).
7.5.3.2 Slave Address Assignment
The seven bit slave address is 001A3A2A1A0x, where A3A2A1A0 is set by the ADDR pin on the device. Bit 0 is the data direction bit, i.e. 001A3A2A1A00 is used for write operation and 001A3A2A1A01 is used for read operation.
7.5.3.3 PMBUS Address Selection
TPS549D22 allows up to 16 different chip addresses for PMBus communication, with the first three bits fixed as 001. The address selection process is defined by the resistor divider ratio from BP pin to ADDR pin, and the address detection circuit will start to work only after VDD input supply has risen above its UVLO threshold. Table 4 lists the divider ratio and some example resistor values. The 1% tolerance resistors with typical temperature coefficient of ±100 ppm/ºC are recommended. Higher performance resistors can be used if tighter noise margin is required for more reliable address detection.
7.5.3.4 Supported Formats
The supported formats are described in the following subsections.
7.5.3.4.1 Direct Format — Write
The simplest format for a PMBus write is direct format. After the start condition [S], the slave chip address is sent, followed by an eighth bit indicating a write. TPS549D22 then acknowledges that it is being addressed, and the master responds with an 8 bit register address byte. The slave acknowledges and the master sends the appropriate 8 bit data byte. Once again the slave acknowledges and the master terminates the transfer with the stop condition [P].
7.5.3.4.2 Combined Format — Read
After the start condition [S], the slave chip address is sent, followed by an eighth bit indicating a write. TPS549D22 then acknowledges that it is being addressed, and the master responds with an 8 bit register address byte. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again, the slave chip address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge followed by previously addressed 8 bit data byte. The master then sends a non-acknowledge (NACK) and finally terminates the transfer with the stop condition [P].
7.5.3.5 Stop Separated Reads
Stop-separated reads can also be used. This format allows a master to set up the register address pointer for a read and return to that slave at a later time to read the data. In this format the slave chip address followed by a write bit are sent after a start [S] condition. TPS549D22 then acknowledges it is being addressed, and the master responds with the 8-bit register address byte. The master then sends a stop or restart condition and may then address another slave. After performing other tasks, the master can send a start or restart condition to the TPS549D22 with a read command. The device acknowledges this request and returns the data from the register location that had been set up previously.
Table 4. ADDR Pin Selection Table
| PMBus_Address<3:0> | CM | RADDR (kΩ) (1% or better and connect to ground) |
|||
|---|---|---|---|---|---|
| 1 | 1 | 1 | 1 | 1: FCCM | Open |
| 0: SKIP | 187 | ||||
| 1 | 1 | 1 | 0 | 1: FCCM | 165 |
| 0: SKIP | 147 | ||||
| 1 | 1 | 0 | 1 | 1: FCCM | 133 |
| 0: SKIP | 121 | ||||
| 1 | 1 | 0 | 0 | 1: FCCM | 110 |
| 0: SKIP | 100 | ||||
| 1 | 0 | 1 | 1 | 1: FCCM | 90.9 |
| 0: SKIP | 82.5 | ||||
| 1 | 0 | 1 | 0 | 1: FCCM | 75 |
| 0: SKIP | 68.1 | ||||
| 1 | 0 | 0 | 1 | 1: FCCM | 60.4 |
| 0: SKIP | 53.6 | ||||
| 1 | 0 | 0 | 0 | 1: FCCM | 47.5 |
| 0: SKIP | 42.2 | ||||
| 0 | 1 | 1 | 1 | 1: FCCM | 37.4 |
| 0: SKIP | 33.2 | ||||
| 0 | 1 | 1 | 0 | 1: FCCM | 29.4 |
| 0: SKIP | 25.5 | ||||
| 0 | 1 | 0 | 1 | 1: FCCM | 22.1 |
| 0: SKIP | 19.1 | ||||
| 0 | 1 | 0 | 0 | 1: FCCM | 16.5 |
| 0: SKIP | 14.3 | ||||
| 0 | 0 | 1 | 1 | 1: FCCM | 12.1 |
| 0: SKIP | 10 | ||||
| 0 | 0 | 1 | 0 | 1: FCCM | 7.87 |
| 0: SKIP | 6.19 | ||||
| 0 | 0 | 0 | 1 | 1: FCCM | 4.64 |
| 0: SKIP | 3.16 | ||||
| 0 | 0 | 0 | 0 | 1: FCCM | 1.78 |
| 0: SKIP | 0 | ||||
7.5.3.6 Supported PMBUS Commands and Registers
Only the following PMBus commands are supported by TPS549D22, and not all parts of each command are supported.
Table 5. PMBUS Command and Register Table
| CMD CODE | COMMAND NAME | DESCRIPTION | NVM? | TYPE | No. of DATA BYTES | BIT PATTERN |
|---|---|---|---|---|---|---|
| 1h | OPERATION | The OPERATION command is used to turn the unit on and off in conjunction with the input from the EN pin. It is also used to cause the device to set the output voltage to the upper or lower Margin voltages. | no | R/W Byte | 1 | 00XX XX00 = Turn Off 1000 XX00 = Turn on (VOUT Margin off) 1001 0100 = Turn on (VOUT Margin Low, Ignore Fault) 1001 1000 = Turn on (VOUT Margin Low, Act on Fault) 1010 0100 = Turn on (VOUT Margin High, Ignore Fault) 1010 1000 = Turn on (VOUT Margin High, Act on Fault) |
| 2h | ON_OFF_CONFIG | Configures the combination of EN pin input and serial bus commands needed to turn the unit on and off. This includes how the unit responds when power is applied. | yes | R/W Byte | 1 | 0001 0011 = Act on neither OPERATION nor EN pin 0001 0111 = Act on EN pin and ignore OPERATION 0001 1011 = Act on OPERATION and ignore EN pin 0001 1111 = Act on OPERATION and Act on EN pin (requires both) |
| 3h | CLEAR_FAULTS | Clears all fault status registers to 0x00 and deasserts SMBAlert. The "Unit is Off" bit in the status byte and "PGOOD# de-assertion" bit in the status word are not cleared when this command is issued. | no | Send Byte | 0 | No data. Write only. |
| 10h | WRITE_PROTECT | Prevents unwanted writes to the device. This register can be over-written. This is not a permanent lock. | yes | R/W Byte | 1 | 1000 0000 Only allow WRITE_PROTECT 0100 0000 Only allow WRITE_PROTECT and OPERATION 0010 0000 Only allow WRITE_PROTECT, OPERATION, ON_OFF_CONFIG and VOUT_COMMAND 0000 0000 Allow all writes |
| 11h | STORE_DEFAULT_ALL | Copies Operating Memory to matching non-volatile Default Store Memory. | no | Send Byte | 0 | No data. Write only. |
| 12h | RESTORE_DEFAULT_ALL | Restores all parameters from non-volatile Default Store Memory to Operating Memory | no | Send Byte | 0 | No data. Write only. |
| 19h | CAPABILITY | This command provides a way for a host system to determine some key capabilities of a PMBus device, including PEC, Alert and Speed. | no | Read Byte | 1 | 1101 0000 = PEC, 1MHz bus speed, ALERT |
| 20h | VOUT_MODE | Hard coded to linear mode with exponent of -9. | no | Read Byte | 1 | 000x xxxx = Linear format. 0001 0111 = Exponent value of -9 (1.953mV resolution) |
| 21h | VOUT_COMMAND | Output voltage setpoint. DAC resolution is 1.9531mV and range is ~0.6V to ~1.200V | yes | R/W Word | 2 | 0000 0001 0011 0011 = 0.5996V 0000 0010 0110 0110 = 1.1992V |
| 25h | VOUT_MARGIN_HIGH | Sets the voltage to which the output is to be changed when the OPERATION command is set to "MARGIN HIGH". | no | R/W Word | 2 | 0000 0001 0011 0011 = 0.5996V 0000 0010 0110 0110 = 1.1992V |
| 26h | VOUT_MARGIN_LOW | Sets the voltage to which the output is to be changed when the OPERATION command is set to "MARGIN LOW". | no | R/W Word | 2 | 0000 0001 0011 0011 = 0.5996V 0000 0010 0110 0110 = 1.1992V |
| 78h | STATUS_BYTE | Status of all fault conditions in a data byte. | no | Read Byte | 1 | See Status Word Table |
| 79h | STATUS_WORD | Status of all fault conditions in two data bytes. | no | Read Word | 2 | See Status Word Table |
| 7Ah | STATUS_VOUT | Returns one byte of information relating to the status of the output voltage related faults. | no | Read Byte | 1 | See Status Vout Table |
| 7Bh | STATUS_OUT | Returns one byte of information relating to the status of the output current related faults. | no | Read Byte | 1 | See Status Iout Table |
| 7Eh | STATUS_CML | Status of communications, logic and memory in a data byte | no | Read Byte | 1 | XXX0 0000 0XX0 0000 = A valid or supported command has been received 1XX0 0000 = An invalid or unsupported command has been received X0X0 0000 = A valid or supported data has been received X1X0 0000 = An invalid or unsupported data has been received XX00 0000 = Packet error check has failed XX10 0000 = Packet error check has succeeded |
| D0h | MFR_SPECIFIC_00 | Customer programmable byte that does not affect chip functionality | yes | R/W Byte | 1 | Free format |
| D1h | MFR_SPECIFIC_01 | Program PGOOD delay and Power-On delay | yes | R/W Byte | 1 | |
| D2h | MFR_SPECIFIC_02 | Read SST, CM, HICLOFF, TRK and SEQ. Program Forced SKIP Soft Start. | yes | R/W Byte | 1 | |
| D3h | MFR_SPECIFIC_03 | Program Fsw and control mode, Read RC ramp | yes | R/W Byte | 1 | |
| D4h | MFR_SPECIFIC_04 | Program the DCAP3 offset | yes | R/W Byte | 1 | |
| D6h | MFR_SPECIFIC_06 | Program the VDD UVLO level | yes | R/W Byte | 1 | |
| D7h | MFR_SPECIFIC_07 | Program the final tracking set point and select pseudo/external tracking | yes | R/W Byte | 1 | |
| FCh | MFR_SPECIFIC_44 | Read TI PMBUS GUI Devcie ID and IC revision code | no | Read Word | 2 |
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Figure 31. Startup and VOUT_COMMAND Timing Diagram
Table 6. Status Word Summary Table
| BITS | NAME | MEANING |
|---|---|---|
| Low 7 | not used | not used |
| Low 6 | OFF | Unit is not providing power to the output |
| Low 5 | VOUT_OV_FAULT | Output overvoltage |
| Low 4 | IOUT_OC_FAULT | Output overcurremt |
| Low 3 | VDD_UV_FAULT | Input VDD undervoltage |
| Low 2 | TEMP | Internal die temperature. Over temperature fault |
| Low 1 | CML | Communications, logic or memory fault |
| Low 0 | OTHER | None of the above in the PMBUS spec |
| High 7 | VOUT | Any output voltage fault or warning |
| High 6 | IOUT | Any output current fault or warning |
| High 5 | VDD_UV_FAULT | Input VDD undervoltage |
| High 4 | not used | Not used |
| High 3 | PGOOD# | Power good de-asserted |
| High 2 | not used | not used |
| High 1 | not used | not used |
| High 0 | not used | not used |
Table 7. Status VOUT Summary Table
| BITS | NAME | MEANING |
|---|---|---|
| 7 | OVF | Over voltage fault |
| 6 | OVW | Over voltage warning |
| 5 | UVW | Under voltage warning |
| 4 | UVF | Under voltage fault |
| 3 | not used | not used |
| 2 | not used | not used |
| 1 | not used | not used |
Table 8. Status IOUT Summary Table
| BITS | NAME | MEANING |
|---|---|---|
| 7 | OCF | Over current fault |
| 6 | OCUVF | Over current and output undervoltage fault |
| 5 | not used | not used |
| 4 | UCF | Negative over current limit |
| 3 | not used | not used |
| 2 | not used | not used |
| 1 | not used | not used |
| 0 | not used | not used |
7.5.4 Register Maps
7.5.4.1 OPERATION Register (address = 1h)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| On_OFF | 0 | OPMARGIN<3:0> | 0 | 0 | |||
| R/W | R/W | R/W | R | R | |||
| RLEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 9. OPERATION
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | ON_OFF | R/W | 0 | 0: Turn off switching converter (if CMD=1) 1: Turn on switching converter (if CMD=1), and also enable VOUT Margin function |
| 6 | R | 0 | ||
| 5:2 | OPMARGIN<3:0> | R/W | 0 | 00xx: Turn off VOUT Margin function 0101: Turn on VOUT Margin Low and Ignore Fault 0110: Turn on VOUT Margin Low and Act On Fault 1001: Turn on VOUT Margin High and Ignore Fault 1010: Turn on VOUT Margin High and Act On Fault |
| 1 | R | 0 | ||
| 0 | R | 0 |
7.5.4.2 ON_OFF_CONFIG Register (address = 2h)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 1 | CMD | CP | 1 | 1 |
| R | R | R | R | R/W | R/W | R | R |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
7.5.4.3 CLEAR FAULTS (address = 3h)
The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command simultaneously clears all bits in all status registers. At the same time, the device clears its SMB_ALERT# signal output if the device is asserting the SMB_ALERT# signal.
The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. If the fault is still present when the bit is cleared, the fault bit shall immediately be set again and the host notified by the usual means.
7.5.4.4 WRITE PROTECT (address = 10h)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| R/W | R/W | R/W | R | R | R | R | R |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 11. WRITE PROTECT
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | WRITE_PROTECT | R/W | 0 | 00000000: Enable writes to ALL commands 00100000: Enable writes to only WRITE_PROTECT, OPERATION and ON_OFF_CONFIG and VOUT_COMMAND commands 01000000: Enable writes to only WRITE_PROTECT and OPERATION 10000000: Enable writes to only WRITE_PROTECT |
7.5.4.5 STORE_DEFAULT_ALL (address = 11h)
Store all of the current storable register settings in the EEPROM memory as the new defaults on power up.
It is permitted to use the STORE_DEFAULT_ALL command while the device is operating. However, the device may be unresponsive during the write operation with unpredictable memory storage results. TI recommends to turn the device output off before issuing this command.
EEPROM programming faults will set the ‘CML’ bit in the STATUS_BYTE and the ‘MEM’ bit in the STATUS_CML registers.
7.5.4.6 RESTORE_DEFAULT_ALL (address = 12h)
Write EEPROM data to those CSRs that: (1) have EEPROM support, and; (2) are unprotected according to current setting of WRITE_PROTECT.
It is permitted to use the RESTORE_DEFAULT_ALL command while the device is operating. However, the device may be unresponsive during the copy operation with unpredictable, undesirable or even catastrophic results. TI recommends to turn the device output off before issuing this command.
No data bytes are sent, just the command code is sent.
7.5.4.7 CAPABILITY (address = 19h)
This command provides a way for a host system to determine some key capabilities of this PMBus device.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PEC=1 | SPEED <1:0> | ALRT=1 | 0 | 0 | 0 | 0 | |
| R | R | R | R | R | R | R | R |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 12. CAPABILITY
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | PEC=1 | R | 1 | 1: Packet Error Checking is supported |
| 6:5 | SPEED <1:0> | R | 10b | 10: Maximum supported bus speed is 1 MHz |
| 4 | ALRT=1 | R | 1 | TPS549D22 has an ALERT# pin and it supports SMBus Alert Response protocol |
| 3 | R | 0 | ||
| 2 | R | 0 | ||
| 1 | R | 0 | ||
| 0 | R | 0 |
7.5.4.8 VOUT_MODE (address = 20h)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MODE = 000 | Exponent = 10111 | ||||||
| R | R | R | R | R | R | R | R |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 13. VOUT_MODE
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | MODE = 000 | R | 0 | 000: Linear Format |
| 4:0 | Exponent | R | 17h | 10111: Exponent = −9 (equivalent of 1.9531 mV/LSB) |
7.5.4.9 VOUT_COMMAND (address = 21h)
The VOUT_COMMAND command sets the output voltage in volts. The exponent is set be VOUT_MODE at –9 (equivalent of 1.9531 mV/LSB). The programmed VOUT is computed as:
The support range for TPS549D22 is: 0.5996 V to 1.1992 V. It is effectively 9-bits limited to 307 to 614 decimal. Slew rate control is provided through MODE pin.
VOUT setps 1 step/tslew, where tslew is programmable by MODE pin: 4, 8, 16, or 32 µs.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Mantissa | |||||||||||||||
| R | R | R | R | R | R | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 14. VOUT_COMMAND
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | Mantissa | R | 0000 | |
| 3:0 | Mantissa | R/W | 00xx | x = pin strap |
| 7:0 | Mantissa | R/W | xxxx xxxx |
7.5.4.10 VOUT_MARGIN_HIGH (address = 25h)
The VOUT_MARGIN_HIGH command loads the TPS549D22 with the voltage to which the output is to be changed when the OPERATION command is set to “Margin High”.
The data bytes are two bytes formatted according to the setting of the VOUT_MODE command.
The support margin range for TPS549D22 is: 0.5996 V to 1.1992 V. It is effectively 9-bits limited to 307 to 614 decimal. Slew rate control is provided through MODE pin.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Mantissa | |||||||||||||||
| R | R | R | R | R | R | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 15. VOUT_MARGIN_HIGH
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | Mantissa | R | 0000 | |
| 3:0 | Mantissa | R/W | 00xx | x = pin strap |
| 7:0 | Mantissa | R/W | xxxx xxxx |
7.5.4.11 VOUT_MARGIN_LOW (address = 26h)
The VOUT_MARGIN_LOW command loads the TPS549D22 with the voltage to which the output is to be changed when the OPERATION command is set to “Margin Low”.
The data bytes are two bytes formatted according to the setting of the VOUT_MODE command.
The support margin range for TPS549D22 is: 0.5996 V to 1.1992 V. It is effectively 9-bits limited to 307 to 614 decimal. Slew rate control is provided through MODE pin.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Mantissa | |||||||||||||||
| R | R | R | R | R | R | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 16. VOUT_MARGIN_LOW:
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | Mantissa | R | 0000 | |
| 3:0 | Mantissa | R/W | 00xx | x = pin strap |
| 7:0 | Mantissa | R/W | xxxx xxxx |
7.5.4.12 STATUS_BYTE (address = 78h)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Not used | OFF | VOUT_OV | IOUT_OC | VDD_UV | TEMP | CML | OTHER |
| R | R | R | R | R | R | R | R |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 17. STATUS_BYTE
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | Not Used | R | N/A | Not Used |
| 6 | OFF | R | N/A | 0: IC is on. This includes the following fault response conditions where the output is still being actively driven, such as OVP and OCF. 1: IC is off. This includes two conditions. One is unit is commanded off via OPERATION/ON_OFF _CONFIG and the other is unit is commanded on via OPERATION/ON_OFF_CONFIG; but, due to fault response the output has been tri-stated by UVF, OT and UVLO. |
| 5 | VOUT_OV | R | N/A | 0: An output overvoltage fault has not occurred 1: An output overvoltage fault has occurred |
| 4 | IOUT_OC | R | N/A | 0: An output overcurrent fault has not occurred 1: An output overcurrent fault has occurred |
| 3 | VDD_UV | R | N/A | 0: An input undervoltage fault has not occurred 1: An input undervoltage fault has occurred |
| 2 | TEMP | R | N/A | 0: A temperature fault or warning has not occurred 1: A temperature fault or warning has occurred |
| 1 | CML | R | N/A | 0: A communications, memory or logic fault has not occurred 1: A communications, memory or logic fault has occurred |
| 0 | OTHER | R | N/A | 0: A fault or warning not listed above has not occurred 1: A fault of warning not listed above has occurred |
7.5.4.13 STATUS_WORD (High Byte) (address = 79h)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VOUT | IOUT | VDD | Not Used | PGOOD# | Not Used | ||
| R | R | R | R | R | R | ||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 18. STATUS_WORD (High Byte)
7.5.4.14 STATUS_VOUT (address = 7Ah)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OVF | OVW | UVW | UVF | Not Used | |||
| R | R | R | R | R | |||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 19. STATUS_VOUT
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | OVF | R | N/A |
0: An output overvoltage fault has not occurred 1: An output overvoltage fault has occurred |
| 6 | OVW | R | N/A | 0: An output overvoltage warning has not occurred 1: An output overvoltage warning has occurred |
| 5 | UVW | R | N/A |
0: An output undervoltage warning has not occurred 1: An output undervoltage warning has occurred |
| 4 | UVF | R | N/A |
0: An output undervoltage fault has not occurred 1: An output undervoltage fault has occurred |
| 3:0 | Not Used | R | N/A | Not Used |
7.5.4.15 STATUS_IOUT (address = 7Bh)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OCF | OCUVF | Not Used | UCF | Not Used | |||
| R | R | R | R | R | |||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 20. STATUS_IOUT
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | OCF | R | N/A |
0: An output positive overcurrent fault has not occurred 1: An output positive overcurrent fault has occurred |
| 6 | OCUVF | R | N/A | 0: A simultaneous output positive overcurrent and undervoltage fault has not occurred 1: A simultaneous output positive overcurrent and undervoltage fault has occurred |
| 5 | Not Used | R | N/A | Not Used |
| 4 | UCF | R | N/A |
0: An output negative overcurrent fault has not occurred 1: An output negative overcurrent fault has occurred |
| 3:0 | Not Used | R | N/A | Not Used |
7.5.4.16 STATUS_CML (address = 7Eh)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COMM | DATA | PEC | Not Used | OTH | Not Used | ||
| R | R | R | R | R | R | ||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 21. STATUS_CML
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | COMM | R | N/A |
0: A valid or supported command has been received 1: An invalid or unsupported command has been received |
| 6 | DATA | R | N/A |
0: A valid or supported data has been received 1: An invalid or unsupported data has been received |
| 5 | PEC | R | N/A |
0: Packet Error Check has failed 1: Packet Error Check has succeeded |
| 4:2 | Not Used | R | N/A | Not Used |
| 1 | OTH | R | N/A |
0: A communication fault other than the ones listed in this table has not occurred 1: A communication fault other than the ones listed in this table has occurred. Currently, this bit is only set for too many data bytes |
| 0 | Not Used | R | N/A | Not Used |
7.5.4.17 MFR_SPECIFIC_00 (address = D0h)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| USER SCRATCH PAD | |||||||
| R/W | |||||||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 22. MFR_SPECIFIC_00
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | USER SCRATCH PAD | R/W | 0 | The MFR_SPECIFIC_00 is a user-accessible register dedicated as a user scratch pad. |
7.5.4.18 MFR_SPECIFIC_01 (address = D1h)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | PGD | POD | ||||
| R | R | R/W | R/W | ||||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 23. MFR_SPECIFIC_01
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | R | 00b | The MFR_SPECIFIC_01 is a user-accessible register dedicated for configuring the PGOOD delay and Power-On Delay functions. (Refer to Table 24 and Table 25) | |
| 5:3 | PGD | R/W | 010b | |
| 2:0 | POD | R/W | 010b |
Table 24. PGD[2:0]
| PGD[2] | PGD[1] | PGD[0] | PGood Delay |
|---|---|---|---|
| 0 | 0 | 0 | 256 µs |
| 0 | 0 | 1 | 512 µs |
| 0 | 1 | 0 | 1.024 ms |
| 0 | 1 | 1 | 2.048 ms |
| 1 | 0 | 0 | 4.096 ms |
| 1 | 0 | 1 | 8.192 ms |
| 1 | 1 | 0 | 16.384 ms |
| 1 | 1 | 1 | 131.072 ms |
Table 25. POD[2:0]
| POD[2] | POD[1] | POD[0] | Power-On Delay |
|---|---|---|---|
| 0 | 0 | 0 | 256 µs |
| 0 | 0 | 1 | 512 µs |
| 0 | 1 | 0 | 1.024 ms |
| 0 | 1 | 1 | 2.048 ms |
| 1 | 0 | 0 | 4.096 ms |
| 1 | 0 | 1 | 8.192 ms |
| 1 | 1 | 0 | 16.384 ms |
| 1 | 1 | 1 | 32.768 ms |
7.5.4.19 MFR_SPECIFIC_02 (address = D2h)
The MFR_SPECIFIC_02 register allows the user to read the configuration of various pinstrap features and/or overwrite them. Note, that any overwritten values here are only good until the next power-on-reset; when all parameters will revert back to their pinstrap configurations.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TRK | SEQ | 0 | FORCESKIPSS | SST | HICLOFF | CM | |
| R/W | R/W | R | R/W | R/W | R/W | R/W | |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 26. MFR_SPECIFIC_02
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | TRK | R/W | P |
This bit indicates whether the device is using internal or external reference voltage tracking. It will initially be loaded and reflect the value of the pinstrap; but, can also be overwritten by PMBus. 1: External tracking. |
| 6 | SEQ | R/W | P |
This bit indicates whether the device is using internal or external soft-start ramp. It will initially be loaded and reflect the value of the pinstrap; but, can also be overwritten by PMBus. 1: Sequencing |
| 5 | R | 0 | ||
| 4 | FORCESKIPSS | R/W | 1 |
This bit (when set) allows the user to force Soft-start to always use SKIP mode; regardless of the CM pinstrap. 1: Soft start is forced to operate in SKIP mode, then CM bit controls the mode after soft start. |
| 3:2 | SST | R/W | P | These bits indicate the time the device takes to ramp the output voltage up to regulation (that is, soft-start). The field will initially be loaded and reflect the value of the pinstrap; but, can also be overwritten by PMBus. (Refer to Table 27) |
| 1 | HICLOFF | R/W | P |
This bit indicates the response the device will take upon an output under-voltage fault. There are two fault response options which are enforced by the analog circuits: Hiccup or Latch-off. The bit value will initially be loaded and reflect the value of the pinstrap; but, can also be overwritten by PMBus. 1: Latch off after UVP fault. |
| 0 | CM | R/W | P |
This bit indicates the conduction mode for the device. The bit value will initially be loaded and reflect the value of the pinstrap; but, can also be overwritten by PMBus. 1: FCCM |
Table 27. SST
| SST[1] | SST[0] | Soft-start time |
|---|---|---|
| 0 | 0 | 1 ms |
| 0 | 1 | 2 ms |
| 1 | 0 | 4 ms |
| 1 | 1 | 8 ms |
7.5.4.20 MFR_SPECIFIC_03 (address = D3h)
The MFR_SPECIFIC_03 register allows the user to read the configuration of the DCAP pinstrap feature (and/or overwrite it); as well configure the Ramp Generator and the PWM switching frequency.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DCAP3 | 0 | RCSP | 0 | FS | |||
| R/W | R | R/W | R | R/W | |||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 28. MFR_SPECIFIC_03 Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | DCAP3 | R/W | P |
This bit allows the user to read/configure the device’s internal DCAP-3 mode. It will initially be loaded and reflect the value of the pinstrap; but, can also be overwritten by PMBus. 0: Internal DCAP3 is disabled (ramp injection is off). 1: Internal DCAP3 is enabled (ramp injection is on) |
| 6 | R | 0 | ||
| 5:4 | RCSP | R/W | P | These bits allow the user to read/configure the D-CAP3 ramp generator’s resistor value selection. (Refer to Table 29) |
| 3 | R | 0 | ||
| 2:0 | FS | R/W | 011b | These bits allow the user to read/configure the device’s PWM switching frequency. (Refer to Table 30) |
Table 29. RCSP
| RCSP[1] | RCSP[0] | Resistor Selection |
|---|---|---|
| 0 | 0 | Resistor ÷ 2 |
| 0 | 1 | Resistor ÷ 1 |
| 1 | 0 | Resistor × 2 |
| 1 | 1 | Resistor × 3 |
Table 30. FS
| FS[2] | FS[1] | FS[0] | Switching Frequency |
|---|---|---|---|
| 0 | 0 | 0 | 315 kHz |
| 0 | 0 | 1 | 425 kHz |
| 0 | 1 | 0 | 550 kHz |
| 0 | 1 | 1 | 650 KHz |
| 1 | 0 | 0 | 825 KHz |
| 1 | 0 | 1 | 900 KHz |
| 1 | 1 | 0 | 1.025 KHz |
| 1 | 1 | 1 | 1.225 MHz |
7.5.4.21 MFR_SPECIFIC_04 (address = D4h)
The MFR_SPECIFIC_04 register allows the user to configure the D-CAP offset reduction and fixed offset correction.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DCAP3OffsetSel | DCAP3Offset[1:0] | 0 | 0 | 0 | 0 | 0 | |
| R/W | R/W | R | R | R | R | R | |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 31. MFR_SPECIFIC_04
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | DCAP3OffsetSel | R/W | 1 |
This bit allows the user to read/configure the D-CAP loop’s offset reduction scheme. 0: Select DCAP loop manual offset reduction circuit. 1: Select DCAP loop automatic offset reduction circuit. |
| 6:5 | DCAP3Offset | R/W | 0 | These bits allow the user to read/configure the D-CAP3 offset correction if and only if DCAP3OffsetSel = 0 (refer to Table 32) |
| 4:0 | R | 0 |
Table 32. DCAP3OFFSET
| DCAP3Offset[1] | DCAP3Offset[0] | Additional Offset Correction Voltage Added |
|---|---|---|
| 0 | 0 | 0 mV |
| 0 | 1 | + 2 mV |
| 1 | 0 | + 4 mV |
| 1 | 1 | + 6 mV |
7.5.4.22 MFR_SPECIFIC_06 (address = D6h)
The MFR_SPECIFIC_06 is a user-accessible register dedicated for configuring the VDD Under-voltage LockOut threshold.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | VDDUVLO[2:0] | ||
| R | R | R | R | R | R/W | ||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 33. MFR_SPECIFIC_06
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:3 | R | 0 |
|
|
| 2:0 | VDDUVLO | R/W | 101b | These bits allow the user to read/configure the device’s VDD Under-voltage Lockout threshold. (Refer to Table 34) |
Table 34. VDDUVLO
| VDDUVLO[2] | VDDUVLO[1] | VDDUVLO[0] | VDD UVLO threshold |
|---|---|---|---|
| 0 | X | X | 10.2 volts |
| 1 | 0 | 0 | 2.8 volts |
| 1 | 0 | 1 | 4.25 volts |
| 1 | 1 | 0 | 6 volts |
| 1 | 1 | 1 | 8.1 volts |
7.5.4.23 MFR_SPECIFIC_07 (address = D7h)
The MFR_SPECIFIC_07 is a user-accessible register dedicated for configuring the device’s PGOOD threshold and external tracking options.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VPBAD | SPARE | 0 | TRKOPTION | VTRKIN[3:0] | |||
| R/W | R/W | R | R/W | R/W | |||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 35. MFR_SPECIFIC_07
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | VPBAD | R/W | 1 |
This bit allows the user to read/configure the PGOOD high and low thresholds. 0: PGOOD high and low thresholds are +16% and -16%, respectively 1: PGOOD high and low thresholds are +20% and -32%, respectively |
| 6 | SPARE | R/W | 0 | This bit allows the user to read/configure an EEPROM backed SPARE bit and corresponding digital block output. 0: pSPARE = 0 1: pSPARE = 1 |
| 5 | R | 0 | ||
| 4 | TRKOPTION | R/W | 0 | This bit allows the user to read/control whether the external TRKIN is enabled by a 425 mV threshold, or not. 0: TRKIN voltage must be above 425mV (that is, TRKINOK = 1) before switcher can be enabled. 1: TRKIN voltage does not need to be above 425mV before switcher can be enabled. |
| 3:0 | VTRKIN | R/W | 1111b | These bits allow the user to read/configure the device’s final TRKIN target voltage for external tracking operation. (Refer to Table 36) |
Table 36. VTRKIN
| VTRKIN[3] | VTRKIN[2] | VTRKIN[1] | VTRKIN[0] | Final TRKIN target voltage for external tracking operation |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 500 mV |
| 0 | 0 | 0 | 1 | 550 mV |
| 0 | 0 | 1 | 0 | 600 mV |
| 0 | 0 | 1 | 1 | 650 mV |
| 0 | 1 | 0 | 0 | 700 mV |
| 0 | 1 | 0 | 1 | 750 mV |
| 0 | 1 | 1 | 0 | 800 mV |
| 0 | 1 | 1 | 1 | 850 mV |
| 1 | 0 | 0 | 0 | 900 mV |
| 1 | 0 | 0 | 1 | 950 mV |
| 1 | 0 | 1 | 0 | 1.00 V |
| 1 | 0 | 1 | 1 | 1.05 V |
| 1 | 1 | 0 | 0 | 1.10 V |
| 1 | 1 | 0 | 1 | 1.15 V |
| 1 | 1 | 1 | 0 | 1.20 V |
| 1 | 1 | 1 | 1 | 1.25 V |
7.5.4.24 MFR_SPECIFIC_44 (address = FCh)
The DEVICE_CODE command returns a 12-bit unique identifier code for the device and a 4 bit device revision code. Device revisions codes should start at 0x0.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Identifier Code | Revision Code | ||||||||||||||
| R | R | R | R | R | R | R | R | R | R | R | R | R | R | R | R |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 37. MFR_SPECIFIC_44
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | Identifier Code | R | 02h |
0000 0010 0000b – Device ID Code Identifier for TPS549D22. |
| 7:4 | R | 0 | ||
| 3:0 | Revision Code | R | 0 | 0000b - Revision Code (first silicon starts at 0) |