The TPS548B27 provides an analog input pin (SS/REFIN) to accept an external reference (a DC voltage source). The device always looks at the voltage on this SS/REFIN pin as the reference for the control loop. When an external voltage reference is applied between the SS/REFIN pin and VSNS– pin, it acts as the reference voltage, so the FB voltage follows this external voltage reference exactly. The same ±0.6% SS/REFIN-to-FB accuracy from the –40°C to 125°C temperature range applies here too.

In the middle of internal power-on delay, a detection circuit senses the voltage on the SS/REFIN pin to tell whether an active DC voltage source is applied. Before the detection happens, the SS/REFIN pin tries to discharge any energy on SS/REFIN capacitors through an internal 120-Ω resistor to AGND. This discharge lasts for 125 μs. Then, within a 32-μs window, the detection circuit compares the SS/REFIN pin voltage with an internal reference equal to 89% of V_INTREF. This discharge operation ensures a SS capacitor with left-over energy will not be wrongly detected as a voltage reference. If the external voltage reference fails to supply sufficient current and hold voltage level higher than 89% of V_INTREF, the SS/REFIN detection circuit will provide the wrong detection result.

If the detection result is that SS/REFIN pin voltage falls below 89% of V_INTREF, which means no external reference is connected, the device first uses the internal fixed V_INTREF as the reference for the PGOOD, V_OUT OVP, and V_OUT UVP thresholds. On this configuration, given the SS/REFIN pin sees a soft-start ramp on this pin, the slower ramp along with the internal fixed soft start and the external soft start determine the start-up of FB. Once both the internal and external soft-start ramp finishes, the power-good signal becomes high after a 1.06-ms internal delay. The whole internal soft-start ramp takes 2 ms to finish. The external soft-start done signal goes high when FB reaches a threshold equal to V_INTREF – 50 mV. The device waits for the PGOOD status transition from low to high, then starts using the SS/REFIN pin voltage, instead of the internal V_INTREF as the reference for PGOOD, V_OUT OVP, and V_OUT UVP threshold.

If the detection result is that the SS/REFIN pin voltage holds higher than 89% of V_INTREF, which means an active DC voltage source is used as an external reference, the device always uses the SS/REFIN pin voltage instead of the internal V_INTREF as the reference for the PGOOD, V_OUT OVP, and V_OUT UVP thresholds. On this configuration, since the SS/REFIN pin sees a DC voltage and no soft-start ramp on this pin, the internal fixed soft start is used for start-up. Once the internal soft-start ramp finishes, the power-good signal becomes high after a 1.06-ms internal delay. The whole internal soft-start ramp takes 2 ms to finish because the soft-start ramp goes beyond V_INTREF.

On this external REFIN configuration, applying a stabilized DC external reference to the SS/REFIN pin before the EN high signal is recommended. During the internal power-on delay, the external reference should be capable of holding the SS/REFIN pin equal to or higher than 89% of V_INTREF, so that the device can correctly detect the external reference and choose the right thresholds for power good, V_OUT OVP, and V_OUT UVP. After the power-good status goes from low to high, the external reference can be set in a range from 0.5 V to 1.2 V. To overdrive the SS/REFIN pin during nominal operation, the external reference has to be able to sink more than 36-μA current if the external reference is lower than the internal V_INTREF, or source more than 12-μA current if the external reference is higher than the internal V_INTREF. When driving the SS/REFIN pin by an external reference through a resistor divider, the resistance of the divider should be low enough to provide the sinking, or sourcing current capability.

The configuration of applying EN high signal first, then applying an external ramp on the SS/REFIN pin as a tracking reference can be achieved, as long as design considerations for power good, V_OUT OVP, and V_OUT UVP have been taken. Please contact Texas Instruments for detailed information about this configuration.

If the external voltage source must transition up and down between any two voltage levels, the slew rate must be no more than 1 mV/μs.