ZHCSGE7A January 2017 – July 2017 TPS548B22
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
-
8 Applications and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1 TPS548B22 1.5-V to 18-V Input, 1-V Output, 25-A Converter
- 8.2.2 Design Requirements
- 8.2.3
Design Procedure
- 8.2.3.1 Switching Frequency Selection
- 8.2.3.2 Inductor Selection
- 8.2.3.3 Output Capacitor Selection
- 8.2.3.4 Input Capacitor Selection
- 8.2.3.5 Bootstrap Capacitor Selection
- 8.2.3.6 BP Pin
- 8.2.3.7 R-C Snubber and VIN Pin High-Frequency Bypass
- 8.2.3.8 Optimize Reference Voltage (VSEL)
- 8.2.3.9 MODE Pin Selection
- 8.2.3.10 Overcurrent Limit Design.
- 8.2.4 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購信息
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RVF|40
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RVF|40
訂購信息
5 Pin Configuration and Functions
RVF Package
40-Pin LQFN-CLIP With Thermal Pad
Top View
Pin Functions
| PIN | I/O/P(1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1, 2, 3 | NU | O | Not used pins. |
| 4 | EN_UVLO | I | Enable pin that can turn on the DC/DC switching converter. Use also to program the required PVIN UVLO when PVIN and VDD are connected together. |
| 5 | BOOT | P | Supply rail for high-side gate driver (boot terminal). Connect boot capacitor from this pin to SW node. Internally connected to BP via bootstrap PMOS switch. |
| 6, 7, 26, 27 | NC | No connect. | |
| 8, 9, 10, 11, 12 | SW | I/O | Output switching terminal of power converter. Connect the pins to the output inductor. |
| 13, 14, 15, 16, 17, 18, 19, 20 | PGND | P | Power ground of internal FETs. |
| 21, 22, 23, 24, 25, | PVIN | P | Power supply input for integrated power MOSFET pair. |
| 28 | VDD | P | Controller power supply input. |
| 29 | DRGND | P | Internal gate driver return. |
| 30 | AGND | G | Ground pin for internal analog circuits. |
| 31 | BP | O | LDO output |
| 32 | FSEL | I | Program switching frequency, internal ramp amplitude and SKIP or FCCM mode. |
| 33 | VSEL | I | Program the initial start-up and or reference voltage without feedback resistor dividers (from 0.6 V to 1.2 V in 50-mV increments). |
| 34 | MODE | I | Mode selection pin. Select the control mode (DCAP3 or DCAP), internal VREF operation, external REFIN and tracking operation and soft-start timing selection. |
| 35 | PGOOD | O | Open drain power-good status signal. |
| 36 | ILIM | I/O | Program overcurrent limit by connecting a resistor to ground. |
| 37 | RESV_TRK | I | Do not connect. |
| 38 | RSN | I | Inverting input of the differential remote sense amplifier. |
| 39 | RSP | I | Non-inverting input of the differential remote sense amplifier. |
| 40 | VOSNS | I | Output voltage monitor input pin. |
(1) I = input, O = output, G = GND