ZHCSFG3B July 2016 – December 2016 TPS546C20A
PRODUCTION DATA.
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AGND | 38 | — | Analog ground return for controller device. Connect this pin to PGND and DRGND at the thermal pad. |
| AVIN | 29 | I | Input power to the controller. Connect a low-impedance bypass with a minimum of 1 µF to PGND. The AVIN voltage is also used for input feed-forward. PVIN and AVIN must be the same potential for accurate short circuit protection. |
| BP3 | 27 | O | Output of the 3.3-V onboard regulator. This regulator powers the controller and should be bypassed with a minimum of 2.2 µF to AGND. The BP3 pin is not designed to power external circuit. |
| BP6 | 28 | O | Output of the 6.5-V onboard regulator. This regulator powers the driver stage of the controller and should be bypassed with a minimum of 2.2 µF to the thermal pad (power-stage ground, essentially PGND). TI recommends using an additional 100-nF (typical) bypass capacitor for reducing ripple on BP6. The low-impedance bypassing of this pin to PGND is critical. |
| BOOT | 7 | I/O | Bootstrap pin for the internal flying high-side driver. Connect a 100-nF (typical) capacitor from this pin to the SW pin. To reduce the voltage spike at SW, a BOOT resistor with a value between 1 Ω to 15 Ω can be placed in series with the BOOT capacitor to slow down turnon of the high-side FET. |
| CNTL | 40 | I | PMBus CNTL pin. See the Supported PMBus Commands section. The CNTL pin has an internal pullup and floats high when left floating. |
| COMP | 37 | O | Output of the error amplifier. Connect compensator network from this pin to the FB pin. |
| DIFFO | 35 | O | Output of the differential remote sense amplifier. This provides remote sensing for output voltage reporting and the voltage control loop. For the loop slave device in a 2-phase configuration, the DIFFO pin can be left floating. |
| DRGND | 26 | — | Power ground return for controller device. This pin should be directly connected to the thermal pad on the PCB board. |
| FB | 36 | I | Feedback pin for the control loop. Negative input of the error amplifier. In 2-phase configuration, the FB pin of the loop slave device should be tied to the BP3 pin. |
| ISHARE | 31 | I/O | Current sharing signal for 2-phase operation. For a stand-alone device, the ISHARE pin can be left floating. |
| PGND | 13 | — | Power stage ground return. These pins are internally connected to the thermal pad. |
| 14 | |||
| 15 | |||
| 16 | |||
| 17 | |||
| 18 | |||
| 19 | |||
| 20 | |||
| PMB_CLK | 5 | I | PMBus CLK pin. See the Supported PMBus Commands section. |
| PMB_DATA | 4 | I/O | PMBus DATA pin. See the Supported PMBus Commands section. |
| PVIN | 21 | I | Input power to the power stage. Low-impedance bypassing of these pins to PGND is critical. |
| 22 | |||
| 23 | |||
| 24 | |||
| 25 | |||
| RESET/PGD | 30 | I/O | This pin is for the output voltage reset or the power-good output. The function of this pin is determined by the user-accessible bit, EN_RESET_B, in the MFR_SPECIFIC_21 (E4h) register. The default of this pin is for the power-good indicator. For output voltage reset, this pin is a logic-low input. An internal pulldown of 750 kΩ is present so this pin requires a pullup resistor to enable the programming of VOUT. As the power-good indicator, this pin is an open-drain output which floats up to external pullup when the device is operation and in regulation. During any fault or warn conditions, this pin is pulled low. For details see Table 4. The PGD pin can be left floating when not used. |
| RSP | 33 | I | The positive input of the remote sense amplifier. For a stand-alone device or the loop master device in a 2-phase configuration, connect the RSP pin to the output voltage at the load. For the loop slave device in a 2-phase configuration, the remote sense amplifier is not required for output voltage sensing or regulation. |
| RSN | 34 | I | The negative input of the remote sense amplifier. For a stand-alone device or the loop master device in a 2-phase configuration, connect the RSN pin to the ground at the load. For the loop slave device in a 2-phase configuration, the remote sense amplifier is not required for output-voltage sensing or regulation. |
| RT | 1 | I | Frequency-setting resistor. Connect a resistor from this pin to AGND to program the switching frequency. Do not leave this pin floating. |
| SMB_ALRT | 6 | O | SMBus™ alert pin. See the Supported PMBus Commands section. |
| SW | 8 | I/O | Switched power output of the device. Connect the output averaging filter and bootstrap capacitor to this group of pins. |
| 9 | |||
| 10 | |||
| 11 | |||
| 12 | |||
| SS | 3 | I | Configures default soft-start time. The SS pin sets default TON_RISE time by connecting a resistor from this pin to AGND. |
| SYNC | 39 | I/O | For frequency synchronization. For the stand-alone device or the loop master device in a 2-phase configuration, with external pullup to the BP6 pin, the SYNC pin will be configured as SYNC-IN pin, and will be synchronized to the rising edge of the external clock applied to this pin. Otherwise, the SYNC pin will be configured as SYNC-OUT pin. For the loop slave device in a 2-phase configuration, the SYNC pin will always be SYNC-IN, and will be synchronized to the falling edge of the incoming clock on SYNC pin. Only 50% duty cycle external clock can be applied to the 2-phase stack to realize the interleaving of 2 phases. Applying an external clock to both the loop master and the loop slave device to synchronize the stack is optional. Without the external clock, the loop master device will output a 50% duty-cycle clock to the loop slave device and the slave device will be synchronized to the falling edge of the clock. The SYNC pin can be left floating when not used. |
| VSEL | 2 | I | Configures default output voltage setting. The VSEL pin sets default output voltage by connecting a resistor from this pin to AGND. |
| VSHARE | 32 | I/O | Voltage sharing signal for 2-phase operation. For stand-alone device, the VSHARE pin can be left floating. |
| Thermal pad | — | Package thermal pad, internally connected to PGND. The thermal pad must have adequate solder coverage for proper operation. | |