ZHCSL73B October 2016 – June 2021 TPS54388C-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4
Device Functional Modes
- 7.4.1 Adjusting the Output Voltage
- 7.4.2 Enable Functionality and Adjusting Undervoltage Lockout
- 7.4.3 Slow-Start or Tracking Pin
- 7.4.4 Sequencing
- 7.4.5 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- 7.4.6 Overcurrent Protection
- 7.4.7 Frequency Shift
- 7.4.8 Reverse Overcurrent Protection
- 7.4.9 Synchronize Using the RT/CLK Pin
- 7.4.10 Power Good (PWRGD Pin)
- 7.4.11 Overvoltage Transient Protection
- 7.4.12 Thermal Shutdown
- 7.4.13 Small-Signal Model for Loop Response
- 7.4.14 Simple Small-Signal Model for Peak-Current-Mode Control
- 7.4.15 Small-Signal Model for Frequency Compensation
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Selecting the Switching Frequency
- 8.2.2.2 Output Inductor Selection
- 8.2.2.3 Output Capacitor
- 8.2.2.4 Input Capacitor
- 8.2.2.5 Slow-Start Capacitor
- 8.2.2.6 Bootstrap Capacitor Selection
- 8.2.2.7 Output-Voltage and Feedback-Resistor Selection
- 8.2.2.8 Compensation
- 8.2.2.9 Power-Dissipation Estimate
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
5 Pin Configuration and Functions
Figure 5-1 RTE Package16-Pin WQFN With Exposed
Thermal PadTop ViewTable 5-1 Pin Functions
| PIN | I/O(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AGND | 5 | — | Connect analog ground electrically to GND close to the device. |
| BOOT | 13 | O | The device requires a bootstrap capacitor between BOOT and PH. A voltage on this capacitor that is below the minimum required by the BOOT UVLO forces the output to switch off until the capacitor recharges. |
| COMP | 7 | O | Error amplifier output, and input to the output-switch current comparator. Connect frequency-compensation components to this pin. |
| EN | 15 | I | Enable pin, internal pullup-current source. Pull below 1.2 V to disable. Float to enable. One can use this pin to set the on-off threshold (adjust UVLO) with two additional resistors. |
| GND | 3 | — | Power ground. Directly connect this pin electrically to the thermal pad under the device. |
| 4 | |||
| PH | 10 | O | The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous) rectifier MOSFET |
| 11 | |||
| 12 | |||
| PWRGD | 14 | O | An open-drain output; asserted low if output voltage is low due to thermal shutdown, overcurrent, over- or undervoltage, or EN shutdown. |
| RT/CLK | 8 | I | Resistor-timing or external-clock input pin |
| SS/TR | 9 | I | Slow start and tracking. An external capacitor connected to this pin sets the output-voltage rise time. Another use of this pin is for tracking. |
| VIN | 1 | I | Input supply voltage, 2.95 V to 6 V |
| 2 | |||
| 16 | |||
| VSENSE | 6 | I | Inverting node of the transconductance (gm) error amplifier |
| Thermal pad | — | Connect the GND pin to the exposed thermal pad for proper operation. Connect this thermal pad to any internal PCB ground planes using multiple vias for good thermal performance. | |
(1) I = input, O = output