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SLUS774C AUGUST 2007 – December 2014 TPS54383 , TPS54386

PRODUCTION DATA.

封裝選項(xiàng)

請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

PWP|14

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

PWP|14
- PPTD393A

訂購(gòu)信息

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

		MIN	MAX	UNIT
Input voltage range	PVDD1, PVDD2, EN1, EN2		30	V
	BOOT1, BOOT2		V_SW+ 7
	SW1, SW2	–2	30
	SW1, SW2 transient (< 50ns)	–3	31
	BP		6.5
	SEQ, ILIM2	–0.3	6.5
	FB1, FB2	–0.3	3
	SW1, SW2 output current		7	A
	BP load current		35	mA
T_J	Operating temperature	–40	+150	°C
	Soldering temperature		+260	°C
T_stg	Storage temperature	–55	165	°C

(1) Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	MAX	UNIT
V_PVDD2	Input voltage		4.5	28	V
T_J	Operating junction temperature		–40	+125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS54383 TPS54386	UNIT
		HTSSOP
		14 PINS
R_θJA	Junction-to-ambient thermal resistance	48.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	29.4
R_θJB	Junction-to-board thermal resistance	25.1
ψ_JT	Junction-to-top characterization parameter	0.9
ψ_JB	Junction-to-board characterization parameter	24.9
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

–40°C ≤ T_J ≤ +125°C, V_PVDD1 = V_PVDD2 = 12 V, unless otherwise noted.

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY (PVDD)
V_PVDD1	Input voltage range			4.5		28	V
V_PVDD2	Input voltage range			4.5		28	V
IDD_SDN	Shutdown		V_EN1 = V_EN2 = V_PVDD2		70	150	μA
IDD_Q	Quiescent, non-switching		V_FB = 0.9 V, Outputs off		1.8	3.0	mA
IDD_SW	Quiescent, while-switching		SW node unloaded; Measured as BP sink current		5		mA
V_UVLO	Minimum turn-on voltage		PVDD2 only	3.8	4.1	4.4	V
V_UVLO(hys)	Hysteresis				400		mV
t_START⁽¹⁾⁽²⁾	Time from startup to softstart begin		C_BP = 10 μF, EN1 and EN2 go low simultaneously		2		ms
ENABLE (EN)
V_EN1	Enable threshold			0.9	1.2	1.5	V
V_EN2	Enable threshold			0.9	1.2	1.5	V
	Hysteresis				50		mV
I_EN1	Enable pull-up current		V_EN1 = V_EN2 = 0 V		6	12	μA
I_EN2	Enable pull-up current		V_EN1 = V_EN2 = 0 V		6	12	μA
t_EN⁽¹⁾	Time from enable to soft-start begin		Other EN pin = GND		10		μs
BP REGULATOR (BP)
BP	Regulator voltage		8 V < P_VDD2 < 28 V	5	5.25	5.6	V
BP_LDO	Dropout voltage		P_VDD2 = 4.5 V; switching, no external load on BP		400		mV
I_BP⁽¹⁾	Regulator external load					2	mA
I_BPS	Regulator short circuit		4.5 V < P_VDD2 < 28 V	10	20	30	mA
OSCILLATOR
f_SW	Switching frequency	TPS54383		255	310	375	kHz
f_SW	Switching frequency	TPS54386		510	630	750	kHz
t_DEAD⁽¹⁾	Clock dead time				140		ns
ERROR AMPLIFIER (EA) and VOLTAGE REFERENCE (REF)
V_FB1	Feedback input voltage		0°C < T_J < +85°C	788	800	812	mV
V_FB2	Feedback input voltage		–40°C < T_J < +125°C	786		812	mV
I_FB1	Feedback input bias current				3	50	nA
I_FB2	Feedback input bias current				3	50	nA
g_M1⁽¹⁾	Transconductance				30		μS
g_M2⁽¹⁾	Transconductance				30		μS
SOFT-START (SS)
T_SS1	Soft-start time			1.5	2.1	2.7	ms
T_SS2	Soft-start time			1.5	2.1	2.7	ms
OVERCURRENT PROTECTION
I_CL1	Current limit channel 1			3.6	4.5	5.6	A
I_CL2	Current limit channel 2		V_ILIM2= V_BP	3.6	4.5	5.6
			V_ILIM2= (floating)	2.4	3.0	3.6
			V_ILIM2= GND	1.15	1.50	1.75
V_UV1	Low-level output threshold to declare a fault		Measured at feedback pin.		670		mV
V_UV2	Low-level output threshold to declare a fault		Measured at feedback pin.		670		mV
T_HICCUP⁽¹⁾	Hiccup timeout				10		ms
t_ON1(oc)⁽¹⁾	Minimum overcurrent pulse width				90	150	ns
t_ON2(oc)⁽¹⁾	Minimum overcurrent pulse width				90	150	ns
BOOTSTRAP
R_BOOT1	Bootstrap switch resistance		From BP to BOOT1 or BP to BOOT2, I_EXT = 50 mA		18		Ω
R_BOOT2	Bootstrap switch resistance		From BP to BOOT1 or BP to BOOT2, I_EXT = 50 mA		18		Ω
OUTPUT STAGE (Channel 1 and Channel 2)
R_DS(on)⁽¹⁾	MOSFET on resistance plus bond wire resistance		T_J = +25°C, V_PVDD2 = 8 V		85		mΩ
R_DS(on)⁽¹⁾	MOSFET on resistance plus bond wire resistance		–40°C < T_J < +125°C, V_PVDD2 = 8 V		85	165	mΩ
t_ON(min)⁽¹⁾	Minimum controllable pulse width		I_SWx peak current > 1 A⁽³⁾		100	200	ns
D_MIN	Minimum Duty Cycle		V_FB = 0.9 V			0	%
D_MAX	Maximum Duty Cycle	TPS54383	f_SW = 300 kHz	90	95		%
D_MAX	Maximum Duty Cycle	TPS54386	f_SW = 600 kHz	85	90		%
I_SW	Switching node leakage current (sourcing)		Outputs OFF		2	12	μA
THERMAL SHUTDOWN
T_SD⁽¹⁾	Shutdown temperature				148		°C
T_SD(hys)⁽¹⁾	Hysteresis				20		°C

(1) Ensured by design. Not production tested.

(2) When both outputs are started simultaneously, a 20-mA current source charges the BP capacitor. Faster times are possible with a lower BP capacitor value. More information can be found in the Input UVLO and Startup section.

(3) See Figure 14 for I_SWx peak current <1 A.