ZHCSAO5B December 2012 – October 2015 TPS51604
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DSG|8
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DSG|8
訂購信息
5 Pin Configuration and Functions
DSG Package
8-Pin WSON
Top View
Pin Functions
| PIN | I/O(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| BST | 1 | I | High-side N-channel FET bootstrap voltage input; power supply for high-side driver |
| DRVH | 8 | O | High-side N-channel gate drive output |
| DRVL | 5 | O | Synchronous low-side N-channel gate drive output |
| GND | 6 | G | Synchronous low-side N-channel gate drive return and device reference |
| PWM | 2 | I | PWM input. A tri-state voltage on this pin turns off both the high-side (DRVH) and low-side drivers (DRVL) |
| SKIP | 3 | I | When SKIP is LO, the zero crossing comparator is active. The power chain enters discontinuous conduction mode when the inductor current reaches zero. When SKIP is HI, the zero crossing comparator is disabled, and the driver outputs follow the PWM input. A tri-state voltage on SKIP puts the driver into a very-low power state. |
| SW | 7 | I/O | High-side N-channel gate drive return. Also, zero-crossing sense input |
| VDD | 4 | I | 5-V power supply input; decouple to GND with a ceramic capacitor with a value of 1 µF or greater |
| Thermal Pad | G | Tie to system GND plane with multiple vias | |
(1) I = Input, O = Output, G = Ground