ZHCSHF4J May 2004 – January 2018 TPS51116
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 VDDQ SMPS, Light Load Condition
- 7.3.2 Low-Side Driver
- 7.3.3 High-Side Driver
- 7.3.4 Current Sensing Scheme
- 7.3.5 PWM Frequency and Adaptive On-Time Control
- 7.3.6 VDDQ Output Voltage Selection
- 7.3.7 VTT Linear Regulator and VTTREF
- 7.3.8 Controling Outputs Using the S3 and S5 Pins
- 7.3.9 Soft-Start Function and Powergood Status
- 7.3.10 VDDQ and VTT Discharge Control
- 7.3.11 Current Protection for VDDQ
- 7.3.12 Current Protection for VTT
- 7.3.13 Overvoltage and Undervoltage Protection for VDDQ
- 7.3.14 Undervoltage Lockout (UVLO) Protection, V5IN (PWP), V5FILT (RGE)
- 7.3.15 Input Capacitor, V5IN (PWP), V5FILT (RGE)
- 7.3.16 Thermal Shutdown
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
- PWP|20
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
6.7 Typical Characteristics
All data in the following graphs are measured from the PWP packaged device.
| DDR2 | VVTT = 0.3 V |
| DCAP Mode | IVDDQ = 7 A |
| DDR | VIN = 12 V |
| DCAP Mode |
| DDR |
| DDR3 | VVLDOIN = 1. 5 V |
| DDR | D021 |
| DDR3 |
| DDR | VVDDQ = 2.5 V |
| fSW = 400 kHz |
| Heavy Load |
| Current mode |
| DDR2 | Sink |
| DCAP Mode | VIN =12 V |
| DDR2 | DCAP Mode |
| DDR2 |
| DDR4 |
| DDR2 |
| DDR4 |
| DDR2 | VVDDQ = 1.8 V |
| fSW = 400 kHz |
| DDR2 | Source |