ZHCS329B July 2011 – April 2015
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Applications and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRY|6
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRY|6
訂購(gòu)信息
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted).(1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Voltage(2) | VCC | –0.3 | 7 | V |
| CT | –0.3 | VCC + 0.3 | ||
| ENABLE, SENSE, SENSE_OUT (push-pull) | –0.3 | 7 | ||
| SENSE_OUT (open drain) | –0.3 | 20 | ||
| SENSE_OUT (push-pull) | –0.3 | 7 | ||
| Current | SENSE_OUT | ±10 | mA | |
| Temperature | Operating junction, TJ | –40 | 125 | °C |
| Storage, Tstg | –65 | 150 | ||
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
7.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VCC | Input supply voltage | 1.7 | 6.5 | V | |
| VENABLE, VENABLE | ENABLE and ENABLE pin voltage | 0 | 6.5 | V | |
| VSENSE | SENSE pin voltage | 0 | 6.5 | V | |
| VSENSE_OUT, VSENSE_OUT (open drain) | SENSE_OUT, SENSE_OUT pin voltage | 0 | 18 | V | |
| VSENSE_OUT, VSENSE_OUT (push-pull) | SENSE_OUT, SENSE_OUT pin voltage | 0 | VCC | V | |
| ISENSE_OUT, ISENSE_OUT | SENSE_OUT, SENSE_OUT pin current | 0.0003 | 1 | mA | |
7.4 Thermal Information
| THERMAL METRIC(1) | TPS389x | UNIT | |
|---|---|---|---|
| DRY (USON) | |||
| 6 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 293.8 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 165.1 | |
| RθJB | Junction-to-board thermal resistance | 160.8 | |
| ψJT | Junction-to-top characterization parameter | 27.3 | |
| ψJB | Junction-to-board characterization parameter | 65.8 | |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 65.8 | |
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
Over the operating temperature range of TJ = –40°C to 125°C, and 1.7 V < VCC< 6.5 V, unless otherwise noted. Typical values are at TJ = 25°C and VCC = 3.3 V.| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| VCC | Supply voltage range | TJ = –40°C to 125°C | 1.7 | 6.5 | V | |||
| TJ = 0°C to 85°C | 1.65 | 6.5 | ||||||
| V(POR) | Power-on reset voltage(1) | VOL (max) = 0.2 V , I(SENSE_OUT) = 15 µA | 0.8 | V | ||||
| ICC | Supply current (into VCC pin) | VCC = 3.3 V , no load | 6 | 12 | µA | |||
| VCC = 6.5 V , no load | 7 | 12 | ||||||
| VIT+ | Positive-going input threshold voltage | V(SENSE) rising | 0.495 | 0.5 | 0.505 | V | ||
| Vhys | Hysteresis voltage | V(SENSE) falling | 5 | mV | ||||
| I(SENSE) | Input current(2) | V(SENSE) = 0 V or VCC | –15 | 15 | nA | |||
| I(CT) | CT pin charge current | 260 | 310 | 360 | nA | |||
| V(CT) | CT pin comparator threshold voltage | 1.18 | 1.238 | 1.299 | V | |||
| R(CT) | CT pin pulldown resistance | 200 | Ω | |||||
| VIL | Low-level input voltage (ENABLE pin) | 0.4 | V | |||||
| VIH | High-level input voltage (ENABLE pin) | 1.4 | V | |||||
| UVLO | Undervoltage lockout(3) | VCC falling | 1.3 | 1.7 | V | |||
| Ilkg | Leakage current | ENABLE = VCC or GND | –100 | 100 | nA | |||
| VOL | Low-level output voltage | VCC ≥ 1.2 V, ISINK = 90 µA (TPS3895/7 only) | 0.3 | V | ||||
| VCC ≥ 2.25 V, ISINK = 0.5 mA | 0.3 | |||||||
| VCC ≥ 4.5 V, ISINK = 1 mA | 0.4 | |||||||
| VOH | High-level output voltage (push-pull) | VCC ≥ 2.25 V, ISOURCE = 0.5 mA | 0.8VCC | V | ||||
| VCC ≥ 4.5 V, ISOURCE = 1 mA | 0.8VCC | |||||||
| Ilkg(OD) | Open-drain output leakage current | V(SENSE_OUT) high impedance = 18 V | 300 | nA | ||||
(1) The lowest supply voltage (VCC) at which output is active (SENSE_OUT is low, SENSE_OUT is high); tr(VCC) > 15 µs/V. Below V(POR), the output cannot be determined.
(2) Specified by design.
(3) When VCC falls below the UVLO threshold, the output deasserts (SENSE_OUT goes low, SENSE_OUT goes high). Below V(POR), the output cannot be determined.
7.6 Timing Requirements
| MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| tpd(r) | SENSE (rising) to SENSE_OUT propagation delay | V(SENSE) rising, C(CT) = open | 40 | µs | ||
| V(SENSE) rising, C(CT) = 0.047 µF | 190 | ms | ||||
| tpd(f) | SENSE (falling) to SENSE_OUT propagation delay | V(SENSE) falling | 16 | µs | ||
| Start-up delay(1) | 50 | µs | ||||
| tw | ENABLE pin minimum pulse duration | 1 | µs | |||
| ENABLE pin glitch rejection | 100 | ns | ||||
| td(OFF) | ENABLE to SENSE_OUT delay time (output disabled) | ENABLE deasserted to output deasserted | 200 | ns | ||
| td(P) | ENABLE to SENSE_OUT delay time (P version) | ENABLE asserted to output asserted delay (P version) |
200 | ns | ||
| td(A) | ENABLE to SENSE_OUT delay time (A version) | ENABLE asserted to output asserted delay (A version), C(CT) = open |
20 | µs | ||
| ENABLE asserted to output asserted delay (A version), C(CT) = 0.047 µF |
190 | ms | ||||
(1) During power on, VCC must exceed 1.7 V for at least 50 µs (plus propagation delay time, tpd(r)) before output is in the correct state.
Figure 1. TPS3895A and TPS3897A Timing
Figure 2. TPS3895P and TPS3897P Timing
Figure 3. TPS3896A and TPS3898A Timing
Figure 4. TPS3896P and TPS3898P Timing
7.7 Typical Characteristics
At TA = 25°C, and VCC = 3.3 V, unless otherwise noted.
(CCT = 47 nF)
(0 mA to 1 mA)
1 mA)
