ZHCSDQ6C April 2015 – March 2024 TPS3702-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VDD | Supply voltage range | 2 | 18 | V | ||
| VIT+(OV) | Positive-going threshold accuracy | VSET ≤ VIL(SET), VSET ≥ VIH(SET) | –0.9% | ±0.25% | 0.9% | |
| VIT–(UV) | Negative-going threshold accuracy | VSET ≤ VIL(SET), VSET ≥ VIH(SET) | –0.9% | ±0.25% | 0.9% | |
| VHYS | Hysteresis voltage(2) | TPS3702xXx | 0.3% | 0.55% | 0.8% | |
| V(POR) | Power-on reset voltage(1) | VOL(max) = 0.25V, IOUT = 15μA | 0.8 | V | ||
| IDD | Supply current | VDD = 2V | 6.0 | 10 | μA | |
| VDD ≥ 5V | 7.0 | 12 | ||||
| ISENSE | Input current, SENSE pin | VSENSE = 5V | 1 | 1.5 | μA | |
| ISET | Internal pull-up current, SET pin | VDD = 18V, SET pin = GND | 600 | nA | ||
| VOL | Low-level output voltage | VDD = 1.3V, IOUT = 0.4mA | 250 | mV | ||
| VDD = 2V, IOUT = 3mA | 250 | |||||
| VDD = 5V, IOUT = 5mA | 250 | |||||
| VIL(set) | Low-level SET pin input voltage | 250 | mV | |||
| VIH(set) | High-level SET pin input voltage | 750 | mV | |||
| ID(leak) | Open-drain output leakage current | VPU = VDD | 300 | nA | ||
| ILKG(od) | VDD = 2V, VPU = 18V | 300 | ||||
| UVLO | Undervoltage lockout(3) | VDD falling | 1.3 | 1.7 | V | |